• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.8
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• pp.1-10
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• 2001

This paper describes new line code algorithm, called NIDI(Nibble Inversion mock Inversion) which is well suited for interconnection and transmission technology, The proposed line code which includes only one redundancy bit serves primary features of line code and synchronization patterns for byte or frame synchronization in interconnection, Also, this line code provides in-band signals and speciaI characters.

• Proceedings of the Korean Society of Computational and Applied Mathematics Conference
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• 2003.09a
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• pp.11-11
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• 2003

오늘날 단일 슈퍼컴퓨터로는 처리가 불가능한 거대한 문제들의 해법이 시도되고 있는데, 이들은 지리적으로 분산된 슈퍼컴퓨터, 데이터베이스, 과학장비 및 디스플레이 장치 등을 초고속 통신망으로 연결한 GRID 환경에서 효과적으로 실행시킬 수 있다. GRID는 1990년대 중반 과학 및 공학용 분산 컴퓨팅의 연구 과정에서 등장한 것으로, 점차 응용분야가 넓어지고 있다. 그러나 GRID 같은 분산 환경은 기존의 단일 병렬 시스템과는 많은 점에서 다르며 이전의 기술들을 그대로 적용하기에는 무리가 있다. 기존 병렬 시스템에서는 주로 동기 알고리즘(synchronous algorithm)이 사용되는데, 직렬 연산과 같은 결과를 얻기 위해 동기화(synchronization)가 필요하며, 부하 균형이 필수적이다. 그러나 부하 균형은 이질 클러스터(heterogeneous cluster)처럼 프로세서들의 성능이 서로 다르거나, 지리적으로 분산된 계산자원을 사용하는 GRID 환경에서는 이기종의 문제뿐 아니라 네트워크를 통한 메시지의 전송 지연 등으로 유휴시간이 길어질 수밖에 없다. 이처럼 동기화의 필요성에 의한 연산의 지연을 해결하는 하나의 방안으로 비동기 반복법(asynchronous iteration)이 나왔으며, 지금도 활발히 연구되고 있다. 이는 알고리즘의 동기점을 가능한 한 제거함으로써 빠른 프로세서의 유휴 시간을 줄이는 것이 목적이다. 즉 비동기 알고리즘에서는, 각 프로세서는 다른 프로세서로부터 갱신된 데이터가 올 때까지 기다리지 않고 계속 다음 작업을 수행해 나간다. 따라서 동시에 갱신된 데이터를 교환한 후 다음 단계로 진행하는 동기 알고리즘에 비해, 미처 갱신되지 않은 데이터를 사용하는 경우가 많으므로 전체적으로는 연산량 대비의 수렴 속도는 느릴 수 있다 그러나 각 프로세서는 거의 유휴 시간이 없이 연산을 수행하므로 wall clock time은 동기 알고리즘보다 적게 걸리며, 때로는 50%까지 빠른 결과도 보고되고 있다 그러나 현재까지의 연구는 모두 어떤 수렴조건을 만족하는 선형 시스템의 해법에 국한되어 있으며 비교적 구현하기 쉬운 공유 메모리 시스템에서의 연구만 보고되어 있다. 본 연구에서는 행렬의 주요 고유쌍을 구하는 데 있어 비동기 반복법의 적용 가능성을 타진하기 위해 우선 이론적으로 단순한 멱승법을 사용하여 실험하였고 그 결과 순수한 비동기 반복법은 수렴하기 어렵다는 결론을 얻었다 그리하여 동기 알고리즘에 비동기적 요소를 추가한 혼합 병렬 알고리즘을 제안하고, MPI(Message Passing Interface)를 사용하여 수원대학교의 Hydra cluster에서 구현하였다. 그 결과 특정 노드의 성능이 다른 것에 비해 현저하게 떨어질 때 전체적인 알고리즘의 수렴 속도가 떨어지는 것을 상당히 완화할 수 있음이 밝혀졌다.

• KIISE Transactions on Computing Practices
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• v.21 no.7
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• pp.476-481
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• 2015

We have parallelized the cumulative sum (CUSUM) test of NIST's statistical random number test suite in a CUDA environment. Storing random walks in an array instead of in scalar variables eliminates data dependence. The change in data structure makes it possible to apply parallel scans, scatters, and reductions at each stage of the test. In addition, serial data exchanges between CPU and GPU are removed by migrating CPU's tasks to GPU. Finally we have optimized global memory accesses. The overall speedup is 23 times over the sequential version. Our results contribute to improving security of random numbers for cryptographic keys as well as reducing the time for evaluation of randomness.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2008.04a
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• pp.313-316
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• 2008

에어컨 시스템은 압축기(Compressor), 응축기(Condenser), 증발기(Evaporator)와 확장밸브(Expansion Valve)로 구성되며, 에어컨 시스템에서 과열도와 저압(증발기의 압력)은 시스템의 효율 증대 및 성능 개선과 안정성에 대하여 결정적인 영향을 미친다. 따라서, 과열도와 저압을 조절하기 위해, 각각의 압축기내의 인버터 주파수와 확장밸브의 개도 제어가 중요하며 선형과 비선형 시스템 모두에 대하여 견실한 성능을 나타내고, 외란에 대하여 강인한 성능을 보이는 퍼지 제어기를 설계한다. 본 논문에서는 과열도와 저압을 제어하기 위하여, 3대의 확장밸브와 1대의 압축기를 가진 에어컨 시스템에 대하여 다중 퍼지 제어기를 설계한다. 또한, 각 제어 플랜트에 대하여 최적의 퍼지 제어기를 설계하기 위하여 3가지 최적화 알고리즘을 사용한다. 즉, 직렬 유전자 알고리즘(Serial Genetic Algorithm; SGA)과 병렬 유전자 알고리즘인 계층적 공정 경쟁 유전자 알고리즘(Hierarchical Fair Competition Genetic Algorithm; HFCGA), 그리고 Particle Swarm Optimization(PSO)을 사용하여 다중 퍼지 제어기를 최적화하고 시뮬레이션의 결과를 비교한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.5
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• pp.484-492
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• 2000

In this paper, a voltage compensator with harmonic current compensating capability is studied and its compensating characteristics are analyzed. Like the hybrid active power filter, the proposed system is composed of parallel LC passive filter and series PWM converter connected to power line through series transformer. It is shown that the compensation of harmonic current generated due to nonlinear loads such as diode rectifier and instantaneous voltage compensation of the source are performed through the proposed compensating system. The operating principle of the proposed system is described through a single-phase equivalent circuit and the control strategy is suggested on the d-q rotating reference frame of the 3-phase system. Also, experiment is carried out to verify compensating characteristics of the proposed system.

• Journal of KIISE:Databases
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• v.32 no.6
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• pp.603-615
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• 2005

As recent business environments are changed and become complex, a more efficient and effective business process management are needed. This paper proposes a new approach to the automatic execution of business processes using Event-Condition-Action (ECA) rules that can be automatically triggered by an active database. First of all, we propose the concept of blocks that can classify process flows into several patterns. A block is a minimal unit that can specify the behaviors represented in a process model. An algorithm is developed to detect blocks from a process definition network and transform it into a hierarchical tree model. The behaviors in each block type are modeled using ACTA formalism. This provides a theoretical basis from which ECA rules are identified. The proposed ECA rule-based approach shows that it is possible to execute the workflow using the active capability of database without users' intervention.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.429-440
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• 2008

As embedded system becomes more complex, software development becomes more important in the entire design process. Most embedded applications consist of multi -tasks, that are executed in parallel. So, dataflow model that expresses concurrency naturally is preferred than sequential programming language to develop multitask software. For the execution of multitasking codes, operating system is essential to schedule multi-tasks and to deal with the communication between tasks. But, it is needed to execute multitasking code without as when the target hardware platform cannot execute as or target platforms are candidates of design space exploration, because it is very costly to port as for all candidate platforms of DSE. For this reason, we propose the serialized multitasking code generation technique from dataflow specification. In the proposed technique, a task is specified with dataflow model, and generated as a C code. Code generation consists of two steps: First, a block in a task is generated as a separate function. Second, generated functions are scheduled by a multitasking scheduler that is also generated automatically. To make it easy to write customized scheduler manually, the data structure and information of each task are defined. With the preliminary experiment of DivX player, it is confirmed that the generated code from the proposed framework is efficiently and correctly executed on the target system.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.3
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• pp.307-312
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• 2013

The interest in reducing the emissions and increasing the fuel economy of ICE vehicles has prompted research on hybrid vehicles, which come in the series, parallel, and power-split types. This study focuses on the series-type hybrid electric vehicle, which has a simple structure. Because each component of a series hybrid vehicle is larger than the corresponding component of the parallel type, the sizing of the vehicle is very important. This is because the performance may be greater or less than what is required. Thus, in this research, the optimal fuel economy was determined and simulated in a real-world system. The optimal sizing was achieved based on the motor, engine/generator, and battery for 13 cycles, where DP was used. The model was developed using ASCET or a Simulink-Amisim Co-simulation platform on the rapid controller prototype, ES-1000.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6A
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• pp.905-912
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• 1999

In this paper we explain a trellis representation of block codes and derive their MAP decoding algorithm based on it. We also analyze the performance of block codes and concatenated codes with block codes as components by computer simulations, which were performed by changing the structures and constituent codes of concatenated codes. Computer simulations show that soft decision decoding of block codes get an extra coding gain than their hard decision decoding and that concatenated codes using block codes have good performance in the case of high code rate.

• KIPS Transactions on Computer and Communication Systems
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• v.7 no.9
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• pp.219-226
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• 2018

One of the systematic ways to generate the number of all cases is a combination to construct a combination tree, and its time complexity is O($2^n$). A combination tree is used for various purposes such as the graph homogeneity problem, the initial model for calculating frequent item sets, and so on. However, algorithms that must search the number of all cases of a combination are difficult to use realistically due to high time complexity. Nevertheless, as the amount of data becomes large and various studies are being carried out to utilize the data, the number of cases of searching all cases is increasing. Recently, as the GPU environment becomes popular and can be easily accessed, various attempts have been made to reduce time by parallelizing algorithms having high time complexity in a serial environment. Because the method of generating the number of all cases in combination is sequential and the size of sub-task is biased, it is not suitable for parallel implementation. The efficiency of parallel algorithms can be maximized when all threads have tasks with similar size. In this paper, we propose a method to efficiently collaborate between CPU and GPU to parallelize the problem of finding the number of all cases. In order to evaluate the performance of the proposed algorithm, we analyze the time complexity in the theoretical aspect, and compare the experimental time of the proposed algorithm with other algorithms in CPU and GPU environment. Experimental results show that the proposed CPU and GPU collaboration algorithm maintains a balance between the execution time of the CPU and GPU compared to the previous algorithms, and the execution time is improved remarkable as the number of elements increases.