• Environmental and Resource Economics Review
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• v.8 no.2
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• pp.245-269
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• 1999

향후 기후변화협약과 같은 환경규제의 강화가 예견되는 상황에서 에너지산업은 상당한 정책변화를 겪게 될 것으로 예상된다. 이러한 정책수립과 결정과정에서 본 연구는 천연가스산업에 대한 정책변화 효과를 분석할 수 있는 일반균형 분석모형을 제시함으로써 천연가스산업에 관한 유용한 정보를 제공할 수 있을 것으로 기대된다. 소국경제를 가정한 연산가능 일반균형모형(CGE)을 통해 분석된 천연가스산업의 거시경제적 파급효과를 살펴보면 다음과 같다. 먼저, 천연가스 가격이 5% 상승하였을 경우에는 실질GDP가 0.031% 감소하고, 생산자 물가지수는 0.051% 상승하였다. 가계수요가 10% 증가한 경우와 투자가 10% 증가한 경우에는 실질 GDP가 각각 0.002%씩 상승하고 생산자 물가지수는 0.008%와 0.004% 상승하는 것으로 나타났다. 이러한 분석결과는 천연가스산업이 비교적 거시경제에 미치는 영향이 적은 것을 보여 주고 있다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10d
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• pp.361-363
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• 2002

Version space는 목표 개념이 속성 값에 대한 제한조건의 연언(conjunction)으로 표현될 수 있는 귀납적 개념학습에서 가설공간을 표현하기 위해 사용된다. Version space의 크기는 속성 값의 수에 대해 지수적으로 증가하는데, 우리는 DNA 분자를 이용하여 version space를 표현하는 효율적인 방법을 제시한다. 또한 version space를 유지하기 위한 기본 연산과, 이를 DNA 분자를 이용하는 구현 방법이 제시된다. 또한 DNA 분자로 표현된 version space를 활용하여 새로운 example에 대한 분류를 예측하는 방법을 제시한다.

• Proceedings of the Korea Multimedia Society Conference
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• 2004.05a
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• pp.61-64
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• 2004

RFID 시스템에서 태그와 리더 사이의 통신은 Radio Frequency를 이용해서 이루어짐으로 공격자에 의해 도청될 수 있으며, 태그의 정보가 노출되면 사용자의 프라이버시 침해 문제를 가져올 수 있다. RFID 태그의 프라이버시를 보호하기 위해 제안된 대부분의 기존 방식들은 태그의 ID를 식별하기 위해 모든 태그에 대한 정보를 가지고 식별 과정을 수행해야 하는 비효율성을 가지고 있다. 본 논문에서는 태그의 출력을 매번 다르게 변화시켜, 태그에 대한 위치 추적을 불가능하게 하고, 3번의 지수연산만으로 해당 태그를 식별할 수 있는 RFID 가변 정보화 방식을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.2
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• pp.33-41
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• 2001

Currently, the compression is one of the most important technology in multimedia society. Audio files arc rapidly propagated throughout internet Among them, the most famous one is MP-3(MPEC-1 Laver3) which can obtain CD tone from 128Kbps, but tone quality is abruptly down below 64Kbps. MPEC-II AAC(Advanccd Audio Coding) is not compatible with MPEG 1, but it has high compression of 1.4 times than MP 3, has max. 7.1 and 96KHz sampling rate. In this paper, we propose an algorithm that decreased the capacity of AAC encoding computation but increased the processing speed by optimizing psychoacoustic model which has enormous amount of computation in MPEG 2 AAC encoder. The optimized psychoacoustic model algorithm was implemented by C++ language. The experiment shows that the psychoacoustic model carries out FFT(Fast Fourier Transform) computation of 3048 point with 44.1 KHz sampling rate for SMR(Signal to Masking Ratio), and each entropy value is inputted to the subband filters for the control of encoder block. The proposed psychoacoustic model is operated with high speed because of optimization of unpredictable value. Also, when we transform unpredictable value into a tonality index, the speed of operation process is increased by a tonality index optimized in high frequency range.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.21-32
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• 2007

Vuillaume-Okeya presented unsigned receding methods for protecting modular exponentiations against side channel attacks, which are suitable for tamper-resistant implementations of RSA or DSA which does not benefit from cheap inversions. The proposed method was using a signed representation with digits set ${1,2,{\cdots},2^{\omega}-1}$, where 0 is absent. This receding method was designed to be computed only from the right-to-left, i.e., it is necessary to finish the receding and to store the receded string before starting the left-to-right evaluation stage. This paper describes new receding methods for producing SPA-resistant unsigned representations which are scanned from left to right contrary to the previous ones. Our contributions are as follows; (1) SPA-resistant unsigned left-to-right receding with general width-${\omega}$, (2) special case when ${\omega}=1$, i.e., unsigned binary representation using the digit set {1,2}, (3) SPA-resistant unsigned left-to-right Comb receding, (4) extension to unsigned radix-${\gamma}$ left-to-right receding secure against SPA. Hence, these left-to-right methods are suitable for implementing on memory limited devices such as smartcards and sensor nodes

• Journal of KIISE:Software and Applications
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• v.32 no.4
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• pp.247-257
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• 2005

Generally, the network topology design problem is characterized as a kind of NP-hard combinatorial optimization problem, which is difficult to solve with the classical method because it has exponentially increasing complexity with the augmented network size. In this paper, we propose the efficient approach with two phase that is comprised of evolutionary computation approach based on Prufer number(PN), which can efficiently represent the spanning tree, and a heuristic method considering 2-connectivity, to solve the highly reliable network topology design problem minimizing the construction cost subject to network reliability: firstly, to find the spanning tree, genetic algorithm that is the most widely known type of evolutionary computation approach, is used; secondly, a heuristic method is employed, in order to search the optimal network topology based on the spanning tree obtained in the first Phase, considering 2-connectivity. Lastly, the performance of our approach is provided from the results of numerical examples.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.391-396
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• 2013

In this paper, for HEVC decoding, an SAO hardware design with less processing time and reduced area is proposed. The proposed SAO hardware architecture introduces the design processing $8{\times}8$ CU to reduce the hardware area and uses internal registers to support $64{\times}64$ CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC $0.18{\mu}m$ library, the gate area is 30.7k and the maximum frequency is 250MHz. The proposed SAO hardware architecture can process the decode of a macroblock in 64 cycles.

• Journal of IKEEE
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• v.20 no.4
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• pp.398-411
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• 2016

SVM, a machine learning method, is widely used in image processing for it's excellent generalization performance. However, to add other data to the pre-trained data of the system, we need to train the entire system again. This procedure takes a lot of time, especially in embedded environment, and results in low performance of SVM. In this paper, we implemented an SVM trainer and classifier in an FPGA to solve this problem. We parlallelized the repeated operations inside SVM and modified the exponential operations of the kernel function to perform fixed point modelling. We implemented the proposed hardware on Xilinx ZC 706 evaluation board and used TSR algorithm to verify the FPGA result. It takes about 5 seconds for the proposed hardware to train 2,000 data samples and 16.54ms for classification for $1360{\times}800$ resolution in 100MHz frequency, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.727-736
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• 2009

In this paper, the $arccos(cos^{-1})$ arithmetic unit for mobile graphics accelerator is designed. The mobile vector graphics applications need tight area, execution time, power dissipation, and accuracy constraints compared to desktop PC applications. The designed processor adopts 2nd-order polynomial approximation scheme based on IEEE floating point data format to satisfy speed and accuracy conditions and reduces area via hardware sharing structure. The arccosine processor consists of 15,280 gates and its estimated operating frequency is about 125Mhz at operating condition of $0.35{\mu}m$ CMOS technology. Because the processor can execute arccosine function within 7 clock cycles, it has about 17 MOPS(million arccos operations per second) execution rate and can be applicable to mobile OpenVG processor. And because of its flexible architecture, it can be applicable to the various transcendental functions such as exponential, trigonometric and logarithmic functions via replacement of ROM and minor hardware modification.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.5
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• pp.81-88
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• 2010

Sun et al. proposed a new design of wearable token system for security of mobile devices, such as a notebook and PDA. In this paper, we show that Sun et al.'s system is vulnerable to off-line password guessing attack and man in the middle attack based on known plain-text attack. We propose an improved scheme which overcomes the weaknesses of Sun et al.'s system. The proposed protocol requires to perform one modular multiplication in the wearable token, which has low computation ability, and modular exponentiation in the mobile devices, which have sufficient computing resources. Our protocol has no security problem, which threatens Sun's system, and known vulnerabilities. That is, the proposed protocol overcomes the security problems of Sun's system with minimal overheads.