• Title/Summary/Keyword: 주파수체배기

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Design for Frequency Tripler Using Novel Bandpass Filter with Low Insertion Loss (낮은 삽입손실을 갖는 새로운 대역통과 필터를 이용한 주파수 3체배기 설계)

  • Min, Jun-Ki;Cho, Seung-Yong;Kim, Hyun-Jin;Kim, Yong-Hwan;Lee, Kyoung-Hak;Kim, Dae-Hee;Yun, Ho-Seok;Hong, Ui-Seok
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.10A
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    • pp.1031-1036
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    • 2006
  • This paper proposes a novel BPF structure with less insertion loss and small size instead of the existing coupled line BPF for the output of the tripler using APDP (Anti-Parallel Diode Pair). This proposed BPF consists of the interdigital capacitor and spiral open stub. The proposed BPF has the insertion loss of less than 0.7dB within the band $(16.41{\sim}19.23GHz)$. The conversion loss of the tripler is about $16.6{\sim}18.5dB$ $(flatness<{\pm}1dB)$ at $5.72{\sim}6.28GHz$ of fundamental frequency. Its fundamental frequency and the fifth harmonic suppression characteristic at 6GHz are -32.16dBc and -44.6dBc, respectively And its phase noise attenuation characteristic is about 9.5dB at 100kHz.

A Study on the Realization of Broadband frequency Multiple VCO for Multi-Band Radar Detector (다중 대역 레이더 탐지기용 광대역 주파수 체배 VCO 구현에 관한 연구)

  • Park Wook-Ki;Kang Suk-Youb;Go Min-Ho;Park Hyo-Dal
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.10A
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    • pp.971-978
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    • 2005
  • In this paper, we design and fabricate a VCO(Voltage Controlled Oscillator) for radar detector of X/K/Ka band using frequency multiplier. The existing VCO operated in radar detector have many Problems such as narrow bandwidth, slow frequency variable rate, unstable of production due to high frequency. So we design and fabricate a VCO improved such problems using frequency multiplier. As a result of measure, investigated frequency multiple VCO show its output power 3.64 dBm at multiplied operating frequency 11.27 GHz and have wide frequency tuning range of 660 MHz by controlled voltage 0V to 4.50 V applied diode. And also its phase noise is -104.0 dEc at 1 MHz offset frequency so we obtain suitable performance for commercial use.

Design and fabrication of the MMIC frequency doubler for 29 GHz local oscillator application (29GHz 국부 발진 신호용 MMIC 주파수 체배기의 설계 및 제작)

  • Kim, Jin-Sung;Lee, Seong-Dae;Lee, Bok-Hyoung;Kim, Sung-Chan;Sul, Woo-Suk;Lim, Byeong-Ok;Kim, Sam-Dong;Park, Hyun-Chang;Park, Hyung-Moo;Rhee, Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.11
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    • pp.63-70
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    • 2001
  • We demonstrate the MMIC (monolithic microwave integrated circuit) frequency doublers generating stable and low-cost 29 GHz local oscillator signals from 14.5 GHz input signals. These devices were designed and fabricated by using the M MIC integration process of $0.1\;{\mu}m$ gate-length PHEMTs (pseudomorphic high electron mobility transistors) and passive components. The measurements showed S11 or -9.2 dB at 145 GHz, S22 of -18.6 dG at 29 GHz and a minimum conversion loss of 18.2 dB at 14.5 GHz with an input power or 6 dBm. Fundamental signal of 14.5 GHz were suppressed below 15.2 dBe compared to the second harmonic signal at the output port, and the isolation characteristics of fundamental signal between the input and the output port were maintained above :i0 dB in the frequency range 10.5 GHz to 18.5 GHz. The chip size of the fabricated MMIC frequency doubler is $1.5{\times}2.2\;mm^2$.

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A Novel Frequency Doubler using Feedforward Structure and DGS Microstrip for Fundamental and High-Order Components Suppression (Feedforward 구조와 DGS를 이용하여 기본 신호와 3차 이상의 고조파 신호를 제거한 2차 주파수 체배기 설계)

  • 황도경;임종식;정용채
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.5
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    • pp.513-520
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    • 2003
  • In this paper, a novel design concept of frequency doubler using feedforward technique and DGS microstrip line is proposed. The feedforward loop plays a role of fundamental frequency suppression and DGS microstrip line suppresses over the 3rd order harmonic components. By using this new concept, the high suppression for the undesired signals could be achieved easily. The proposed technique is experimentally demonstrated in 1.87 GHz-to-3.74 GHz frequency doubler. The output power of -3 dBm at the frequency of 3.74 GHz(2f$\_$0/) is measured with 42.9 dB suppression of the fundamental frequency signal(f$\_$0/), 20.2 dB suppression of the 3rd harmonic signal(3f$\_$0/) and B9.7 dB suppression of the 4th harmonic signal(4f$\_$0/). The conversion loss of -2.34 dB ∼ -5.8 dB at the bandwidth of 100 MHz, the phase noise of -97.51 dB/Hz(@10 kHz) were measured.

Ring Hybrid Balun with Good Amplitude and Phase Balance and Its Application to a Balanced Frequency Doubler (진폭과 위상 특성을 개선한 링 하이브리드 결합기를 사용한 평형 주파수 체배기 회로)

  • Na, Won;Lee, Moon-Que
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.7
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    • pp.713-718
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    • 2008
  • A modified broad-band ring hybrid balun with additional two shorted $\lambda$/4 stubs is proposed. The proposed balun is a modified version which has additional two shorted $\lambda$/4 stubs to compensate phase and amplitude imbalances of conventional ring hybrid coupler. To demonstrate the validity of the proposed balun, a balanced Schottky-diode frequency doubler is designed and measured. Measurement data show that the proposed frequency doubler has around 10 dB conversion loss and more than 30 dB fundamental suppression over an input range of $1.6{\sim}2.35\;GHz$.

A study on the PLL oscillator for Wireless CATV (무선 CATV를 위한 PLL 발진기 설계 및 제작 연구)

  • 장준혁;이용덕;류근관;이민희;오일덕;홍의석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.11B
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    • pp.1858-1863
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    • 2000
  • 본 논문에서는 SPD(Sampling Phase Detector)를 이용한 위상고정 방법의 무선 CATV용 위상 고정 유전체 공진 발진기(PLDRO)를 설계·제작하였다. 이 발진기는 하이브리드 형태인 12.875 GHz의 VCDRO(Voltage Controlled Dielectric Resonator Oscillator)와 완충 증폭기, 방향성 결합기, 주파수 체배기, 샘플링 위상 검출기, 루프 필터, 기준 주파수 발진기, VHF 증폭기로 구성되어 있다. 위상 고정 유전체 공진 발진기의 발진출력은 25.75 GHz에서 1.17 dBm, 기본주파수 억압 -27.83 dBc로 안정된 위상고정 상태를 나타내었다. 이때의 위상잡음은 -101.7 dBc/Hz @ 100KHz로 측정되었다.

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Design of 77 GHz Radar Transmitter Using 13 GHz CMOS Frequency Synthesizer and Multiplier (13 GHz CMOS 주파수 합성기와 체배기를 이용한 77 GHz 레이더 송신기 설계)

  • Song, Ui-Jong;Kang, Hyun-Sang;Choi, Kyu-Jin;Cui, Chenglin;Kim, Seong-Kyun;Kim, Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.11
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    • pp.1297-1306
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    • 2012
  • This work presents a 77 GHz radar transmitter for the automotive radar system. An integrated 13 GHz frequency synthesizer fabricated using 130 nm RF CMOS process drives a commercial W-band compound semiconductor monolithic multifunction amplifier(MPA), which includes a frequency multiplier by six to generate 77 GHz transmitting signal. The 13 GHz frequency synthesizer includes a high efficiency injection buffer of 4 dBm output power to drive the MPA. The output power of 77 GHz radar transmitter is higher than 13.99 dBm and the magnitude of the reference spur relative to the carrier is -36.45 dBc. The phase noise is -81 dBc/Hz at 1 MHz offset frequency from the carrier.

A Design of Muti-Octave Ultra Wideband Frequency Synthesizer (멀티 옥타브 초광대역 주파수 합성기 설계)

  • Shin, Geum-Sik;Koo, Bon-San;Lee, Moon-Que
    • Proceedings of the KIEE Conference
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    • 2004.07c
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    • pp.2017-2019
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    • 2004
  • 본 논문에서는 S/C-밴드(2${\sim}$8GHz)에서 동작하는 초광대역 주파수 합성기를 설계하였다. 먼저 S-밴드(2-4GHz) 광대역 전압제어발진기를 가지고 획득시간을 단축하기 위한 연산 증폭기를 사용한 DA변환기와 능동루프 필터(Active Loop Filter)로 구성된 S-밴드 주파수 합성기를 설계하였다. 그리고 주파수 체배기, SPDT RF 스위치를 통합하여 최종적으로 S/C-밴드 초광대역 주파수 합성기를 설계하였다. 제작된 주파수 합성기는 200kHz 비교주파수에서 위상잡음은 100kHz 옵셋 주파수에서 -92dBc/Hz이하, 불요주파수 특성은 -62.33dBc 이하, 획득시간은 1.3ms 이하로 측정되었다.

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