• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제18권6호
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• pp.220-229
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• 2004

The AC railway system is quite differing from the general electric power system because it is single- phase and intermittently heavy loads. Thus, inevitably power quality problems are occurred in the AC railway system, i.e. voltage regulation voltage sags, voltage imbalance, and harmonic distortion. Recently, the power quality of the AC railway system becoming a hot issue because it is affect the control and safety of high-speed traction. In addition it is also affect the power quality of the electric power system. In this paper, single-phase Unified Power Quality Conditioner(UPQS) for the AC railway system is proposed to compensate the voltage sags and harmonic distortion. The configurations and control schemes of the proposed single-phase UPQC are presented. The effectiveness of the proposed single-phase UPQC application is verified by the PSCAD/EMTDC simulation works. It can be shown that the application of UPQC in the AC railway system is very useful to compensate the voltage sags and harmonic distortion from the results of related simulation works.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제23권6호
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• pp.40-51
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• 2009

To analyze influences under open faults in switching devices of the PWM inverter and under the isolation between the inverter and motor terminal, a faulty model for the inverter-driven permanent magnet synchronous motor is presented. Even though the conventional dq motor model obtained through the transformation of phase voltage model is widely used to analyze and control AC motor, it can not be used under open faults in switching devices since the 3-phase balanced condition is no longer hold under the open fault and it is not easy to obtain motor input voltages in open phase from the pole voltage. To deal with this problem, a faulty model for an inverter-driven permanent magnet synchronous motor is derived by using the line voltage of motor according to switch open, which can be effectively used for performance evaluation of the diagnostic algorithm. The validity of the proposed faulty model is verified through comparative simulations and experiments using DSP TMS320F28335.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제23권12호
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• pp.191-200
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• 2009

This paper, which consists of two parts, dealt with the parameter tuning of the power system stabilizer for a 612[MVA] thermal power plant in KEPCO system and its validation in field test. In Part 1 of the paper, the selection of parameters such as lead-lag time constants for phase compensation, system gain was optimized by using linear & eigenvalue analyses and they were verified through the time-domain transient stability analysis. In part 2, the performance of PSS was finally verified by the generator's on-line field test. Through the comparisons of simulation results and measured data before and after tuning of the PSS, the models of generator and its controllers including AVR, Governor and PSS used in the simulation are validated and confirmed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제29권8호
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• pp.18-22
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• 2015

Digitalization of the substation in Korea has been in progress so far with focusing on Station Bus. However, its application to Process Bus has been delayed due to some technical issues. IEDs based on Process Bus use the data values of SV and GOOSE. As the size of communication data on Process Bus is comparatively bigger than that of Station Bus, it is very important for the evaluating the performance of Process Bus to analyze the transferring speed and quality of data from the first equipment, which is located on process level, to station level. According to the results of related studies, it is said that the most important factor for the design and operation of Process Bus network is the communication delay with consideration of the volume of packets. In the paper, the results of performance test for the network with and without application of VLAN on Process Bus system that uses integrated IEDs are presented. Additionally, the paper proposes the optimal method to analyze the communication delays of network systems through evaluating the maximum delay time, link process ratio and the amount of lost packets by using a simulation tool.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제22권6호
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• pp.14-17
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• 2008

This paper describes the simulation of a phase splitter for the design of Chireix Outphasing power amplifier. Phase splitter separate the input signal with $0[^{\circ}]$ into the signal with $+90[^{\circ}]$ and $-90[^{\circ}]$ Chireix Outphasing power amplifier get a linearized output from the signal amplifying and combining the separated signal with the phase of $+90[^{\circ}]$ and $-90[^{\circ}]$ of the phase splitter. phase splitter is the core device when designing Chireix Outphasing power amplifier. It is very difficult to design phase splitter with the difference of $90[^{\circ}]$. This phase splitter is used to design the difference of $180[^{\circ}]((90[^{\circ}]+{\alpha}),\;-(90[^{\circ}])+{\alpha}))$ using simulation tool and a differential amplifier.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제22권6호
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• pp.26-33
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• 2008

This paper presents a new full-bridge soft switching PWM DC-DC converter circuit topology that adding one switcher, one lossless snubber quasi-resonance capacity to power source for general welding machine This full-bridge soft switching DC-DC convoter· topology can applicable 600[V] switching device (IGBT)incase of AC 400[V] common power source because the voltage of active switcher is 1/2 of DC bus line voltage. And low voltage hight current out)ut that first coil current is smaller than second coil current in high frequency transformer can be obtained with decreasing path loss in conventional DC bus line switcher. As it operate ZCS/ZVS in full range, high frequency, high efficiency and high output are implemented at low voltage and high DC current switching power supplies. All of this items are got from simulation and the result of experiment. If make up for the weak points of this proposed circuit, it will be used more easily for next generation TIG, MIG and MAG type of arc-welding machine.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제22권6호
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• pp.34-43
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• 2008

The state-space average model is extended to buck-boost, and buck-boost topology switching mode DC/DC converters and modified to have higher precision without increment of computation. The modified model is used in continuous conduction mode(CCM) switching DC/DC converters and some significant conclusions are derived. This paper discusses the discontinuous conduction mode(DCM) modeling of DC/DC converter and critical characteristic using average model of switch. Average model of switch approach is expended to the modeling of boundary conduction mode DC/DC converters that operate at the boundary between continuous conduction mode(CCM) and discontinuous conduction mode(DCM). Frequency responses predicted by the average model of switch are verified by simulation and experiment. A prototype featuring 15[V] input voltage, 24[V] output voltage, and 24[W] output power using MOSFET.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제22권9호
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• pp.94-102
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• 2008

Capacitor switching is essential for the economic operation and proper voltage control of KOREA electric utility distribution system. Voltage transients produced by capacitor switching (around 2.0 per unit at substation and 2.5 or less per unit at customer site, and lasting less then 1[ms]) do not have the magnitude or duration to interfere with the operation of computers, but they do disrupt the operation of adjustable speed drivers. The result of our research, ASD manufacturers should learn from the computer industry and design products that will operate satisfactory In the electrical envelopment in which they will be placed. In this case history, the inductors on the input to ADSs in order to prevent nuisance tripping from capacitor switching(and other causes within the apartment) proved to be an effective, low-cost solution.

• Journal of Digital Convergence
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• 제14권4호
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• pp.419-424
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• 2016

In this paper, we studied a light distribution for the LED chips arrangement using an optical design software. The structures of the edge type LED luminaires are reflector plane, LGP(lighting guide plane) and diffuse plane. The reflector plane is on the middle of the overall structure. We had simulation that placing LED chips on the reflector center of the reflector edge by changing the position of LED chips above the reflector center at 1mm, 2mm, and 3mm respectively. In the case, when LED chips are on the center of the reflector, it shows the light distribution of the general diffuse illumination, the semi-direct distribution with 0.56 efficiency and the direct distribution with 0.31 efficiency. And the wedge type LGP shows more efficiency than the flat type. Gradually increasing shape of semi-spherical type by 0.015mm has power of 1.02W, efficiency of 0.25, and maximum luminous intensity of 0.104W/sr, it also and shows the better optical characteristics than the reflector plane that have no patterns. This semi-spherical type shows the better optical characteristics than the reflector plane that have no patterns.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제12권2호
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• pp.829-834
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• 2011

Exposure process is the most important technology to fabricate highly integrated circuit. Up to now, mask type lithography process has been generally used. However, it is not efficient for small quantity and/or frequently changing products. Therefore, maskless lithography technology is raised in exposure process. In this study, relations between multi-beam energy and overlay were analyzed. Exposure experiment of generating pattern was performed. It was from presented scan line by multi- beam simulation. As a result, optimal scan line distance was proposed by simulation, and micro pattern accuracy could be improved by exposure experiment using laser direct imaging system.