• Journal of KIISE:Information Networking
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• v.29 no.4
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• pp.375-385
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• 2002

The IETF has defined the Intserv model and the RSVP signaling protocol to improve QoS capability for a set of newly emerging services including voice and video streams that require high transmission bandwidth and low delay. However, since the current Intserv model requires each router to maintain the states of each service flow, the complexity and the overhead for processing packets in each rioter drastically increase as the size of the network increases, giving rise to the scalability problem. This motivates our work; namely, we investigate and devise new control schemes to enhance the scalability of the Intesev model. To do this, we basically resort to the SCORE network model, extend it to fairly well adapt to the three services presented in the Intserv model, and devise schemes of the QoS scheduling, the admission control, and the edge and core node architectures. We also carry out the computer simulation by using ns-2 simulator to examine the performance of the proposed scheme in respects of the bandwidth allocation capability, the packet delay, and the packet delay variation. The results show that the proposed scheme meets the QoS requirements of the respective three services of Intserv model, thus we conclude that the proposed scheme enhances the scalability, while keeping the efficiency of the current Intserv model.

• Journal of KIISE:Information Networking
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• v.36 no.4
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• pp.339-350
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• 2009

In wireless sensor networks, the limited battery resources of sensor nodes have a direct impact on network lifetime. To reduce unnecessary power consumption, it is often the case that only a minimum number of sensor nodes operate in active mode while the others are kept in sleep mode. In such a case, however, the network service can be easily unreliable if any active node is unable to perform its sensing or communication function because of an unexpected failure. Thus, for achieving reliable sensing, it is important to maintain the sensing level even when some sensor nodes fail. In this paper, we propose a new fault-tolerance scheme, called FCP(Fault-tolerant Coverage Preserving), that gives an efficient way to handle the degradation of the sensing level caused by sensor node failures. In the proposed FCP scheme, a set of backup nodes are pre-designated for each active node to be used to replace the active node in case of its failure. Experimental results show that the FCP scheme provides enhanced performance with reduced overhead in terms of sensing coverage preserving, the number of backup nodes and the amount of control messages. On the average, the percentage of coverage preserving is improved by 87.2% while the additional number of backup nodes and the additional amount of control messages are reduced by 57.6% and 99.5%, respectively, compared with previous fault-tolerance schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.