• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• The Journal of the Acoustical Society of Korea
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• v.19 no.3
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• pp.51-56
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• 2000

Is this paper, we studied on the automatic speech control system in real-time windows environment using voice recognition. The applied reference pattern is the variable DMS model which is proposed to fasten execution speed and the one-stage DP algorithm using this model is used for recognition algorithm. The recognition vocabulary set is composed of control command words which are frequently used in windows environment. In this paper, an automatic speech period detection algorithm which is for on-line voice processing in windows environment is implemented. The variable DMS model which applies variable number of section in consideration of duration of the input signal is proposed. Sometimes, unnecessary recognition target word are generated. therefore model is reconstructed in on-line to handle this efficiently. The Perceptual Linear Predictive analysis method which generate feature vector from extracted feature of voice is applied. According to the experiment result, but recognition speech is fastened in the proposed model because of small loud of calculation. The multi-speaker-independent recognition rate and the multi-speaker-dependent recognition rate is 99.08% and 99.39% respectively. In the noisy environment the recognition rate is 96.25%.

• Journal of the Korea Society of Computer and Information
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• v.18 no.4
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• pp.183-190
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• 2013

Many researchers in the 21st century has found that robot education is effective to develop the learners' creativity and problem-solving ability. However, the robot education can only be applied to the students whose computer skills are high. Also it can be taught in the well-prepared computer classroom. Students have to learn machine language to control their robots, and robots are controlled by different types of software. Therefore this study has constructed command-based programming blocks to do a robot programming without computers. It also presents a prototype of the programming process and a technological method to combine the command and the programming blocks. We used the blocks which are similar with something in flow chart: to support intuition, and to help students transfer what they learned. And types of blocks and details are described for the Robot Programing Education. Combination of command blocks is made by RS-485 connection method and, it is designed to intercommunicate with connected blocks. It also presents a prototypes: of the programming process using designed command blocks, and of the possibility of Unplugged Robot Education System.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.7 no.1
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• pp.99-104
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• 2012

In this paper, implementation of a wireless video security system relates to a situation outside of using infrared sensors to detect changes when using Zigbee network security in the area of the sensor sends information to the server. The server can judge the situation if an emergency situation through the IP network security camera shot of the area to be transferred command to pantilte. The camera images and information in the security area, sent to administrator's smartphone users to control the camera can see the situation and More than a small video security system was designed so that user can monitor the security zone. Finally, for real-time to identify and respond to emergency situations based on the available wireless networks for video surveillance systems were verified through research and implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2956-2962
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• 2015

In this paper, we propose a novel algorithm, Concentric-Circle Tracing algorithm, which recognizes finger's shape and counts the number of fingers of hand using low-cost web-camera. We improve algorithm's usability by using low-price web-camera and also enhance user's comfortability by not using a additional marker or sensor. As well as counting the number of fingers, it is possible to extract finger's shape information whether finger is straight or folded, efficiently. The experimental result shows that the finger gesture can be recognized with an average accuracy of 95.48%. It is confirmed that the hand-gesture is an useful method for HCI input and remote control command.

• The Journal of the Korea Contents Association
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• v.13 no.11
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• pp.541-550
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• 2013

Generally in case of tablet PC's, the Windows 8 is used to support various functions or development convenience, however it cannot support real-time processing. In addition, existing commercial solutions and RTiK has a problem to support real-time processing due to impossibility of getting APIC timer count value which is used to generate timer interrupt separated from that of Windows. Thus, in this paper, we set the initial APIC count value using MSR_FSB_FREQ to support real-time processing on the Windows 8-based tablet PC's. Additionally, we deal with designing and implementing RTiK+ providing real-time processing to guarantee interrupt periods by controlling C-State which is used for low power techniques. To evaluate the performance of the proposed RTiK+, we measured the periods of generated real-time threads using RDTSC instructions which return the number of CPU clock ticks, and verified that RTiK+ operates correctly within the error ranges of 1ms.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.741-751
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• 2000

To achieve high performance by exploiting instruction level parallelism aggressively in superscalar processors, it is necessary to overcome the limitation imposed by control dependences and data dependences which prevent instructions from executing parallel. Value prediction is a technique that breaks data dependences by predicting the outcome of an instruction and executes speculatively its data dependent instruction based on the predicted outcome. In this paper, a hybrid value prediction scheme with dynamic classification mechanism is proposed. We design a hybrid predictor by combining the last predictor, a stride predictor and a two-level predictor. The choice of a predictor for each instruction is determined by a dynamic classification mechanism. This makes each predictor utilized more efficiently than the hybrid predictor without dynamic classification mechanism. To show performance improvements of our scheme, we simulate the SPECint95 benchmark set by using execution-driven simulator. The results show that our scheme effect reduce of 45% hardware cost and 16% prediction accuracy improvements comparing with the conventional hybrid prediction scheme and two-level value prediction scheme.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.1
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• pp.17-23
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• 2006

In recent years, RFID has received much attention because of spread usage in industrial applications including factory, material flow, logistics and defense areas. However, there is only CRC-16 for error detection in ISO/IEC 18000-6 Protocols prepared for 860-960 MHz RFID, high error rates are expected in cases of high level of security and noisy envirionment. In this paper, we propose a usage of convolution code as a method for satisfying the high level of security requirement and system error performance.'1'he signal control function is implemented in a microprocessor with RF modulation and the convolutional encoding and Viterbi decoding are implemented in an FPGA chip.'The frame error rates are measured with and without convolution coding under the channel conditions of line-of- sight and non line-of-sight, respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.356-365
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• 2002

Test systems verify and classify the various kinds of semiconductor products. So test systems need programs that can test the various special functions of hardware modules and products. Programs can be modified, compiled and executed by engineers. Consequently, the systems needs programming languages that can be easily programmed by engineers and their compilers that can compile and execute teat programs. In this paper we discuss the environment of programming languages and their compilers for the existing domestic teat systems. We design a programming language and implement its compiler that can be conveniently used by the experienced engineers in the industry field. Experimental results show that a newly designed test system with our programming language and compiler can teat products faster than the existing test system.