• The KIPS Transactions:PartC
• /
• v.8C no.5
• /
• pp.557-564
• /
• 2001

Many people use Linux and FreeBSD because it is freeware and excellent performance. The open source code is very important feature but it also has some problem which may be attacked by hackers frequently. This paper describes the SecuROS of secure operating system that is best solution to this problem and introduces user and programmer interface for active use of secure operating system. Developed secure operating system is composed of the access control method MAC and ACL and conforms to the POSIX which is universally used.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2017.04a
• /
• pp.280-282
• /
• 2017

최근 소프트웨어에 내장된 취약점 분석을 위한 자동화 도구 개발 연구가 각 분야에서 활발히 연구되고 있다. 그 중 바이너리 코드를 대상으로 바로 보안취약점을 분석하는 방법이 아닌 중간언어를 활용하여 분석하는 방법이 대두되고 있으며 이를 위한 다양한 중간언어가 제시되었다. 그 중 하이레벨 언어 수준의 내용의 기술이 가능하며 명령어 자체적으로 자료형을 유지하여 보안 취약점 분석에 효과적인 언어로 SIL 중간언어가 재조명 받고 있다. 따라서 본 논문에서는 이룰 위해서 x86/64 기반 어셈블리어를 SIL 로 효과적으로 변환하며 프로그램의 의미가 변하지 않는 것을 확인하기 위해서 프로그램의 제어흐름을 시각화하는 기능을 가진 시스템을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.54-60
• /
• 2006

In order to test the board with IEEE 1149.1 boundary scan design, the test sequence must be applied as the bit stream However it is very tedious job to generate the test bit sequence since it requires the complete hlowledge about the 1149.1. This fuper introduces a convenient PCI/USB interface controller, named as Test-Ready PCI (TRPCI) ard Test-Ready USB (TRUSB). Test Bus Controller has been developed by TI and Lucent aiming to generate the test bit stream as an instruction level, thus even the novice test engineer can easily generate the test sequence.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.77-86
• /
• 2010

This paper presents an efficient secure scan design technique which is based on a fake key and IEEE 1149.1 instruction to protect secret key from scan-based side channel attack for an Advanced Encryption Standard (AES) core embedded on an System-on-a-Chip (SoC). Our proposed secure scan design technique can be applied to crypto IP core which is optimized for applications without the IP core modification. The IEEE 1149.1 standard is kept, and low area, low power consumption, very robust secret-key protection and high fault coverage can be achieved compared to the existing methods.

• The Journal of the Korea Contents Association
• /
• v.19 no.2
• /
• pp.469-476
• /
• 2019

Robotic motion is designed by the rotation and the translation of multiple joint coordinates in a three-dimensional space. Joint coordinates are generally modeled by homogeneous transform matrix. However, the complexity of three dimensional motions prefers the visualization methods based on simulation environments in which models and generated motions work properly. Many simulation environments have the limitations of usability and functional extension from platform dependency and interpretation of predefined commands. This paper proposes the web-based three dimensional simulation environment toward high user accessibility. Also, it covers the small size web server that is linked with Python script. The non linearities of robot control apply to verify the computing efficiency, the process management, and the extendability of user scripts.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.42 no.4 s.304
• /
• pp.59-68
• /
• 2005

In this paper, we design a PCI Express controller for future communication system The controller supports the full functionality of Transaction Layer and Data Link Layer of PCI Express. The designed controller has the proposed transmitter buffer architecture to obey Replay mechanism. This scheme merges the transmitting buffer and the replay buffer. The proposed buffer has the higher data transfer efficiency than the conventional buffer architecture because it can dynamically adjust size of a replay buffer space. We also design transmitter of Transmitter Transaction Layer to effectively support the proposed buffer, The receiver device of PCI Express must possess the buffer for three types of transaction to support Flow Control. And it must report the amount of the buffer space regularly to the Port at the opposite end of the link. We propose the simple receiver buffer scheme using only one buffer to easily support Flow Control. And the designed controller is verified under proposed test bench

• Journal of KIISE
• /
• v.42 no.6
• /
• pp.713-722
• /
• 2015

As open-source software (OSS) becomes more widely used, many users breach the terms in the license agreement of OSS, or reuse a vulnerable OSS module. Therefore, a technique needs to be developed for investigating if a binary program includes an OSS module. In this paper, we propose an efficient technique to detect a particular OSS module in an executable program using its function-level features. The conventional methods are inappropriate for determining whether a module is contained in a specific program because they usually measure the similarity between whole programs. Our technique determines whether an executable program contains a certain OSS module by extracting features such as its function-level instructions, control flow graph, and the structural attributes of a function from both the program and the module, and comparing the similarity of features. In order to demonstrate the efficiency of the proposed technique, we evaluate it in terms of the size of features, detection accuracy, execution overhead, and resilience to compiler optimizations.

• Journal of KIISE:Computer Systems and Theory
• /
• v.33 no.8
• /
• pp.455-476
• /
• 2006

An avatar script language consists of commands set which is used to control avatar behaviors in cyberspace. The script language should be abstract from complex low-level concepts, so that a user can write down a scenario script easily without concerning about physical motion parameters. Also, the script should be defined in a standard format and structure to allow reusing in various implementation tools. In this paper, a layered script language is proposed for avatar behavior representation and control, which consists of task-level behavior, high-level motion and primitive motion script language. The script language of each layer represents behavior elements for a scenario scripting interface, an avatar motion sequence, and geometric information of implementation environment, respectively. Therefore, a user can create a scenario script by abstract behavior interface and a script can be applied to various implementations by the proposed translating process. A presentation domain is chosen for applying the proposed script language and the implementation result shows that the script is flexibly applied in several applications.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.12
• /
• pp.47-58
• /
• 1999

As the performance of processors improves, cache memories are used to overcome the difference of speed between processors and main memories. Generally cache memories are embedded and small sizes, fault coverage is a more important factor than test time in testing point of view. A new test algorithm and a new BIST architecture are developed to detect various fault models with a relatively small overhead. The new concurrent BIST architecture uses the comparator of cache management blocks as response analyzers for tag memories. A modified scan-chain is used for pre-testing of comparators which can reduce test clock cycles. In addition several boundary scan instructions are provided to control the internal test circuitries. The results show that the new algorithm can detect SAFs, AFs, TFs linked with CFs, CFins, CFids, SCFs, CFdyns and DRFs models with O(12N), where N is the memory size and the new BIST architecture has lower overhead than traditional architecture by about 11%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.281-284
• /
• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.