• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.6
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• pp.465-471
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• 2007

The system efficiency of the proposed Buck-Boost AC-DC converter is increased by soft switching method. The converter includes to merit of power factor correction (PFC) from sinusoidal control of input current. The switching behavior of control switches operates with soft switching by partial resonance, and then the proposed converter has high system efficiency with decrement of switching power loss. The input current waveform in proposed converter is got to be a sinusoidal form of discontinuous quasi-pulse row in proportion to magnitude of AC input voltage under the constant duty cycle switching. Therefore, the input power factor is nearly unity. The output voltage of the converter is regulated by PWM control technique. The discontinuous mode action of current flowing into inductor makes to simplify control method and control components. The proposed PFC Buck-Boost converter is analyzed to compare with the conventional PFC Buck-Boost converter. Some computer simulative results and experimental results confirm to the validity of the analytical results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.312-320
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• 2003

This work describes an 8b 200 MHz 0.18 urn CMOS analog-to-digital converter (ADC) based on a pipelined architecture for flat panel display applications. The proposed ABC employs an improved bootstrapping technique to obtain wider input bandwidth than the sampling tate of 200 MHz. The bootstrapuing technique improves the accuracy of the input sample-and-hold amplifier (SHA) and the fast fourier transform (FFT) analysis of the SHA outputs shows the 7.2 effective number of bits with an input sinusoidal wave frequency of 500 MHz and the sampling clock of 200 MHz at a 1.7 V supply voltage. Merged-capacitor switching (MCS) technique increases the sampling rate of the ADC by reducing the number of capacitors required in conventional ADC's by 50 % and minimizes chip area simultaneously. The simulated ADC in a 0.18 um n-well single-poly quad-metal CMOS technology shows an 8b resolution and a 73 mW power dissipation at a 200 MHz sampling clock and a 1.7 V supply voltage.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.9
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• pp.893-900
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• 2016

Output response for prototype system is analyzed according to the pole locations and the damping ratio changes. The system modeling is constructed for RLC-circuit and the output response is analyzed for both a unit-step and a sinusoidal input. The survey is conducted to estimate the understanding ability on the automatic control. A high understanding ability is shown up in analysing the transfer functions of control system. And improvement is manifest in the ability to understand the output response according to the parameter changes. But some difficulty is revealed in acquiring the output responses in time domain.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.4
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• pp.339-345
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• 2002

This paper presents a portable power supply equipped with a battery charger. The proposed system can be operated separatedly distinguishing between DC/AC and AC/DC function. The former uses a battery and the latter a line voltage as the power source to operate on an inverter and a battery charger, respectively. To keep the output voltage being sinusoidal and to have the high dynamic performances even In the cases of load variations, a proper control method is adapted. The operational principles and analysis are explained in detail. The validity of the proposed system is proved from the experimental results.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.1815-1816
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• 2006

소음은 환경 오염원의 하나로서 사람에게 육체적, 정신적 피해를 발생시킨다. 이에 소음 제어 기술의 필요성이 증대하였고, 그 중에서 제어가 까다롭고 고비용을 요구하는 저주파 소음 제어 기술의 개발이 확대되고 있다. 따라서 본 연구에서는 저주파의 주기적인 특성을 가지는 1차원 평면파 소음에 대한 능동 제어를 위해 기존의 적응 피드포워드 방법의 단점을 보완하는 적응 피드백 방법을 이용한 능동 소음 제어 시스템을 구성하고 능동 소음 제어 실험을 수행하였다. 이를 위해 소음원과 제어 음원을 가지는 덕트 형상의 실험 장치를 구성하였다. 제어기 설계를 위해 전파 소음을 예측하는 선형 예측법을 적용한 적응 디지털 필터를 구성하였으며 적응 알고리즘으로 Filtered-X LMS 알고리즘을 이용하였다. 제어기는 제어 알고리즘을 프로그램화하여 DSP에 입력함으로써 구성하였다. 실험에 사용된 소음은 500[Hz] 이하의 단일 주파수의 정현파 소음을 사용하였으며, 실험결과 음압 감소의 효과를 볼 수 있었다. 능동 소음 제어의 기술을 개발하여 하드웨어(덕트)의 모양 및 구조, 제어기의 종류 및 처리 속도, 주파수나 크기와 같은 특성이 급격히 변하는 소음의 경우에 능동적으로 소음을 제어할 수 있으며, 저주파 소음을 발생시키는 관형 연소기와 같은 장치 및 여러 분야에 응용이 가능하도록 하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1325-1331
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• 1996

In this paper, a new current-memory circuit is proposed that reduces the clock feedthrough(CFT) error voltage causing total harmonic distortion(THD) increment in switched-current(SI) systems. Using PMOS transistor in CMOS complementary, the proposed one reduces output distortion current due to the CFT errorvoltage. A proposed current-memory is designed using a 1.2.mu.m CMOS process anda 1MHz sinusoidal signal having a 68.mu.A amplitude current is applied as input (sampling frequency:20MHz). It hasbeen shown from the simulation that the output distortion current effected by the CFT error voltage is reduced by approximately 10 times the error voltage of conventional one, THD is -57dB in case ofappling 1kHz frequency input signalwith 0.5 peak signal-to-bias current ratio.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.5
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• pp.466-476
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• 2011

In this paper, a high-performance current control for the single-phase PWM converter under distorted source voltages is proposed using a composite observer. By applying the composite observer, the fundamental and high-order harmonic components of the source voltage and current are extracted without a delay. The extracted fundamental component is used for a phase-lock loop (PLL) system to detect the phase angle of the source voltage. A multi-PR (proportional-resonant) controller is employed to regulate the single-phase line current. The high-order harmonic components of the line current are easily eliminated, resulting in the sinusoidal line current. The simulation and experimental results have verified the validity of the proposed method.

• Proceedings of the KIPE Conference
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• 2008.10a
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• pp.25-28
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• 2008

본연구는 부스트형 대기압 플라즈마 전원장치에 대한 연구로서 부스트형 전원장치는 플라즈마의 발생을 원활하게 하기위해 커패시터로 모델링되는 부하단에 인가되는 전압을 직접 제어하는 방식을 의미한다. 기존의 정현파 공진형 전원장치는 PWM기법을 이용하여 펄스의 폭을 증감하는 방식으로 전압의 크기를 제어하지만 이 방식은 별도의 공진회로를 이용하여 공진을 일으킨 다음 이를 부하에 인가하는 방식으로 구성되기 때문에 속응성이 떨어지고 균일한 플라즈마를 발생시키기 어렵다. 부스트형 전원장치는 별도의 부스트 컨버터로 직류전압을 제어하여 부하단에 입력되는 전압을 직접 제어하므로 매우 균일한 플라즈마를 발생시킬 수 있는 이점이 있으나 별도의 부스트용 스위치가 필요하고 이로 인한 효율의 감소 및 사이즈의 증가가 되는 문제점이 생긴다. 본 연구에서는 커패시터로 모델링되는 부하를 이용하여 직접 공진을 일으키고 공진된 부하 전압을 직접 부스트 스위치에 인가시키는 방식으로 부스트용 스위치의 소프트 스위칭이 가능한 새로운 방식을 개발하였다. 개발된 방식에서는 부스트용 스위치가 ZCS형태로 켜지고 ZVS형태로 꺼지는 특성을 갖게 되므로 별도의 추가 회로 없이도 획기적인 효율 증가와 방열판 사이즈의 감소로 인한 제품의 경량화가 가능한 장점이 있다. 또한, DC링크 커패시터의 최소화로 인하여 부하단의 아크 문제가 자동적으로 해결되는 장점도 있다. 제안된 제어 방식은 시뮬레이션과 실험으로 그 타당성을 입증하였다.

• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.180-182
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• 2001

Input Current Correction of Single-Phase Buck Rectifier is studied in the paper. To sinusoidal waveform the input current with a near-unity power factor over a wide variety of operating conditions, the output capacitor is operated with voltage reversibility for the supply by arranging the auxiliary diode and power switching device. Then the output voltage is superposed on the input voltage during on time duration of power switching devices in order to minimize the input current distortion caused by the small input voltage when changing the polarity. The tested setup, using two insulated-gate bipolar transistors(IGBT) and a microcomputer, is implemented and IGBT are switched with 20[kHz], which is out of the audible band. Moreover, a rigorous state-space analysis is introduced to predict the operation of the rectifier. The simulated results confirm that the input current can be sinusoidal waveform with a near-unity power factor and a satisfactory output voltage regulation can be achieved.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.6-12
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• 1984

The basic binary quantized first-order digital phase locked loop (DPLL) is modified in order to reduce the aquisition time and steadyftate phase error. Adding the loop that corrects the phase difference by detecting the falling zero-crossing time, an effort for the improving the performance is performed and the performance compared with that of the basic DPLL. Using a graphical method, the phase locking processes of the modified DPLL for a phase step and a frequency step input are depicted visually in the absence of noise. The performance of the modified DPLL for a sinusoidal input added narrow band random noise is evaluated using the Chapman-Kolmogorov equation. This approach is verified by direct computer simulation. The steady-state phase error and the average aquisition time of the modified DPLL are compared with those of the basic DPLL, It is shown that the aquisition time of the modified DPLL is shortened about twice, also, as signal to noise ratio increases, the effect of the modification increases and the steady-state phase error approaches to zero.