• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.147-155
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• 2005

For the last several decades, many researches have been performed to distribute bandwidth fairly between sessions. In this problem, the most important challenge is to realize a scalable implementation and high fairness simultaneously. Here high fairness means that bandwidth is distributed fairly even in short time intervals. Unfortunately, existing scheduling algorithms either are lack of scalable implementation or can achieve low fairness. In this paper, we propose a scheduling algorithm that can achieve feasible fairness without losing scalability. The proposed algorithm is a Hierarchical Deficit Round-Robin (H-DRR). While H-DRR requires a constant time for implementation, the achievable fairness is similar to that of Packet-by-Packet Generalized Processor Sharing(PGPS) algorithm. PGPS has worse scalability since it uses a sorted-priority queue requiring O(log N) implementation complexity where N is the number of sessions.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.80-80
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• 2009

패키징 구조의 발전이 점차 중요한 문제로 대두되어, 칩의 집적 기술의 발전에 따라 실장기술에서도 고속화, 소형화, 미세피치화, 고정밀화, 고밀도화가 요구되고있다. 최근 선진국을 중심으로 전자 전기기기 및 부품의 실장기술에서도 환경 친화적인 기술을 요구함에 따라, 저에너지 공정 및 무연 실장 기술에 대한 연구가 활발하게 진행되고 있다. 기존의 SOP(Small Out-line Package), QFP(Quad Flat Package) 등은 소형화, 다핀화, 고속화, 실장성에 한계가 있기 때문에, SMT(Surface Mount Technology) 형식으로 된 BGA(Ball Grid Array)가 휴대형 전화를 비롯한 기타 전자 부품 실장에 널리 사용되고 있다. BGA ball shear 법은 BGA 모듈의 생산 및 취급 중에 발생할지도 모르는 기판에 수평으로 작용하는 기계적인 전단력에 BGA solder ball이 견딜 수 있는 정도를 측정하기 위해 사용되는 시험법이다. 전단 시험에 의한 전단 강도의 측정 외에 전기전도도 측정, 파면 관찰, 이동거리(displacement), 유한요소 해석법 등을 병행하여 시험법의 신뢰성 향상에 대한 연구가 이루어지고 있다. 본 실험에서는 지름이 $500{\mu}m$인 Sn-3.5Ag 솔더볼을 이용하여 세라믹 기판을 접합하여 BGA 패키지를 완성하였다. 상부 기판에 솔더볼을 정렬시켜 리플로우 방법으로 접합 한 후 솔더볼이 접합된 상부 기판과 하부 기판을 접합 하여 시편을 제작하였다. 접합된 시편들은 $150^{\circ}C$에서 0~800시간 열처리를 실시하였고, 열처리를 하면서 각각 $3{\times}10^2A/cm^2,\;5{\times}10^3A/cm^2$의 전류를 인가하였다. 시편들을 전단 시험기를 이용하여 솔더볼의 기계적 특성 평가를 하였으며, 계면 반응을 관찰하였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.172-175
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• 2011

높은 효율을 가진 비디오 압축 코덱인 H.264/AVC는 예전보다 압축 성능을 향상 시키기 위한 방법 중 하나로 율-왜곡 최적화 기법이라는 것을 사용한다. 이 기법은 압축된 결과를 가지고 손실과 압축률 두 가지를 모두 고려하여 어떤 경우가 더 최적의 압축인가 하는 것을 판별하는데, 여기서 모든 경우에 대해 압축을 수행해야 함으로 이전 보다 몇 배나 높은 복잡도를 가질 수 밖에 없다. 이러한 문제를 해결하고자 하는 노력으로 본 논문에서는 SAHTD(Sum of Absolute Hadamard Transform Difference)라는 기준을 사용하여 이를 이용해 율-왜곡 최적화 기법을 사용하지 않거나, 사용을 최소화 하면서 압축 효율을 유지하는 방법을 제시하였다. 본 논문에서는 휘도 신호 $8{\times}$8과 $4{\times}4$블록을 위한 방법을 제시하고 있다. 이 두 가지 크기의 블록에 대해서 SAHTD값을 구해 SAHTD가 낮은 순으로 모드들을 정렬하고, 이것이 가장 낮은 3개의 모드를 선택해 이것 중에 MPM이 포함되지 않았을 경우에 대해서는 MPM을 포함해 4개의 모드를 선택해 압축을 수행하도록 한다. 여기서 얻은 모드들 중에 SAHTD값이 일정 값 이상 더 낮은 모드가 존재할 경우, 그 모드들에 대해서만 율-왜곡 최적화 기법을 수행한다. 이를 통해 최적의 모드일 가능성이 낮은 모드들에 대한 부가적인 연산 수행을 방지하게 된다. 휘도신호 16x16이나 색차 신호 압축의 경우에는 SAHTD를 사용하여 가장 낮은 SAHTD값을 갖는 모드를 최적의 모드로 결정한다. JM 참조 소프트웨어를 통한 실험결과 제안된 기법은 기존 JM의 방식에 비해 화면 내 프레임의 부호화 시간의 82.2% 감소와 0.042dB의 PSNR 감소율, 0.527%의 비트 증가율을 보여주었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12A
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• pp.1191-1199
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• 2008

We propose the Staggered-zone Resource Allocation (SRA) in order to relax throughput decrease problems by the co-channel interference of the cell boundary users at the cellular OFDMA system using frequency reuse factor K=1 and analyze the throughput improvement. The proposed algorithm allocates the resources to the users in compliance with resource allocation rule which is planned in order to minimize co-channel interference between cells without any additional information. The resource allocation method in the SRA lines up the users in pathloss order as descending series, and then allocates from pre-determined resource allocation region where decides differently in each cell. This algorithm prevents the co-channel interferences of the cell boundary user to be caused by using same resource simultaneously and equalizes interference to the users in the cell.

• Journal of Life Science
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• v.25 no.3
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• pp.357-367
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• 2015

With the ongoing development of next-generation sequencing (NGS) platforms and advancements in the latest bioinformatics tools at an unprecedented pace, the ultimate goal of sequencing the human genome for less than $1,000 can be feasible in the near future. The rapid technological advances in NGS have brought about increasing demands for statistical methods and bioinformatics tools for the analysis and management of NGS data. Even in the early stages of the commercial availability of NGS platforms, a large number of applications or tools already existed for analyzing, interpreting, and visualizing NGS data. However, the availability of this plethora of NGS data presents a significant challenge for storage, analyses, and data management. Intrinsically, the analysis of NGS data includes the alignment of sequence reads to a reference, base-calling, and/or polymorphism detection, de novo assembly from paired or unpaired reads, structural variant detection, and genome browsing. While the NGS technologies have allowed a massive increase in available raw sequence data, a number of new informatics challenges and difficulties must be addressed to improve the current state and fulfill the promise of genome research. This review aims to provide an overview of major NGS technologies and bioinformatics tools for NGS data analyses.

• Journal of the Korea Society of Computer and Information
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• v.18 no.5
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• pp.35-42
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• 2013

Shot boundary detection is an essential step for efficient browsing, sorting, and classification of video data. Robust shot detection method should overcome the disturbances caused by pixel brightness and object movement between frames. In this paper, two shot boundary detection methods are presented to address these problem by using segmentation, object movement, and pixel brightness. The first method is based on the histogram that reflects object movements and the morphological dilation operation that considers pixel brightness. The second method uses the pixel brightness information of segmented and whole blocks between frames. Experiments on digitized video data of National Archive of Korea show that the proposed methods outperforms the existing pixel-based and histogram-based methods.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.6
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• pp.121-132
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• 2005

In the formation of images in a camera, the exposure time is appropriately adjusted to obtain a good image. Hence for a successful alignment of a sequence of images to the same scene, it is required to compensate the different exposure times. If we have no knowledge regarding the exposure time, then we should develop an algorithm that can compensate an image with respect to a reference image without using any camera formation models. In this paper, an exposure compensation is performed by designing predictors based on the conditional expectation between the reference and input images. Further, an adaptive predictor design is conducted to manage the irregular exposure or histogram problem. In order to alleviate the blocking artifact and the overfitting problems in the adaptive scheme, a smoothing technique, which uses the pixels of the adjacent blocks, is proposed. We successfully conducted the exposure compensation using real images obtained from digital cameras and the transmission electron microscopy.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.21-29
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• 2020

The use of NAND flash memory is continuously increased with the demand of mobile data in the IT industry environment. However, the erase operations in flash memory require longer latency and higher power consumption, resulting in the limited lifetime for each cell. Therefore, frequent write/erase operations reduce the performance and the lifetime of the flash memory. In order to solve this problem, management techniques for improving the performance of flash based storage by reducing write and erase operations of flash memory with using disk buffers have been studied. In this paper, we propose a CPWL to minimized the number of write operations. It is a disk buffer management that separates read and write pages according to the characteristics of the buffer memory access patterns. This technique increases the lifespan of the flash memory and decreases an energy consumption by reducing the number of writes by arranging pages according to the characteristics of buffer memory access mode of requested pages.

• Journal of Information Technology and Architecture
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• v.9 no.4
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• pp.455-464
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• 2012

Due to the recent data explosion, methods which can meet the requirement of large data analysis has been studying. This paper proposes MRIterativeBUC algorithm which enables efficient computation of large data cube by distributed parallel processing with MapReduce framework. MRIterativeBUC algorithm is developed for efficient iterative operation of the BUC method with MapReduce, and overcomes the limitations about the storage size and processing ability caused by large data cube computation. It employs the idea from the iceberg cube which computes only the interesting aspect of analysts and the distributed parallel process of cube computation by partitioning and sorting. Thus, it reduces data emission so that it can reduce network overload, processing amount on each node, and eventually the cube computation cost. The bottom-up cube computation and iterative algorithm using MapReduce, proposed in this paper, can be expanded in various way, and will make full use of many applications.

• Journal of the Korean Vacuum Society
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• v.7 no.2
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• pp.88-93
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• 1998

The fabrication process and emission characteristics of gated silicon field emitter arrays(FEAs) using chemical-mechanical-polishing (CMP) method are described. Novel fabrication techniques consisting of two-step dry etching with oxidation of silicon and CMP processes were developed for the formation of sharp tips and clear-cut edged gate electrodes, respectively. The gate height and aperture could be easily controlled by varying the polishing time and pressure in the CMP process. We obtained silicon FEAs having self-aligned and clear-cut edged gate electrode opening by eliminating the dishing problem during the CMP process with an oxide mask layer. The tip height of the finally fabricated FEAs was about 1.1 $\mu$m and the end radius of the tips was smaller than 100 $\AA$. The emission current meaured from the fabricated 2809 tips array was about 31 $\mu$A at a gate voltage of 80 V.