• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.9 s.351
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• pp.6-13
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• 2006

In this paper, we studied vehicle to vehicle (VTV) communication system using DSRC of 5.8 GHz bands. Nowadays, in the road traffic system is going intelligent and advancing, communication between driving vehicle is very important technology for ITS. We can contrive smoothness and safety traffic flowing by exchanging information about velocity, location, braking and driving condition of nearby vehicles. Therefore, we developed and verified the system which required for the communication among vehicles using DSRC technology of 5.8 GHz band hasa 1 Mbps data rate in the high mobility condition. For this, we developed DSRC modem, data link layer and logic link layer to make it possible that communication between vehicles of perfectly operation, and developed application service program for VTV communication. We performed to communication test in the general road and ascent road. In case of the general mad, obtained VTV communication results are more than number of 17 with in 300 m LOS coverage, and total communication time are $2.34{\sim]18.7$ msec that considered maximum 8-transaction. We blow that obtained results can be used VTV communication or the in areas form the feasibility road test as a function or various conditions. In the future, this system is very useful of advanced safety vehicle (ASV) and super smart vehicle system (SSVS) and so on.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.6
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• pp.1-11
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• 2000

In this paper, we propose a novel control signaling protocol that efficiently controls connection setup and increases the utilization of network resources. The proposed protocol, Separated Control Signaling Protocol(SCSP), separates bearer control from call control lot WDM optical networks. The main function of call control is to check the availability of network resources such as wavelengths and receivers at destination node. Bearer control is to reserve and assign wavelengths. The signaling architecture of this protocol consists of call controller and hearer controller The call controller handles call setup and release, activates the beater controller, and manages the status of call and bearer. The bearer controller reserves wavelengths, sets up bearer, tears down bearer. and notifies the status of beater to call controller. The state transition diagrams of each controller are designed. Using control messages and related primitives, the information flows for call setup and bearer setup, hearer teardown and call release, and reaction for setup failures are described to evaluate the performance. The simulation results show that the separated control signaling protocol is superior to conventional one in terms of call blocking probability and resource utilization.

• Journal of IKEEE
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• v.11 no.4
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• pp.158-164
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• 2007

In this study, three types of a novel Trench IGBTs(Insulated Gate Bipolar Transistor) are proposed. The first structure has P-collector which is isolated by $SiO_2$ layer to enhance anode-injection-efficiency and enable the device to have a low on-state voltage drop(Von). And the second structure has convex P-base region between both gates. This structure may be effective to distributes electric-field crowded to gate edge. So this structure can have higher breakdown voltage(BV) than conventional trench-type IGBT(TIGBT). The process and device simulation results show improved on-state, breakdown and switching characteristics in each structure. The first one was presented lower on state voltage drop(2.1V) than that of conventional one(2.4V). Also, second structurehas higher breakdown voltage(1220V) and faster turn off time(9ns) than that of conventional structure. Finally, the last one of the proposed structure has combined the two structure (the first one and second one). This structure has superior electric characteristics than conventional structure about forward voltage drop and blocking capability, turnoff characteristics.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.26-39
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• 2007

In recent years, rate control is an important technique in real time video communication applications using H.264/AVC. Many existing rate control algorithms employ the quadratic rate-distortion model, which is determine the target bits for each P frame. In this paper, a new rate control algorithm for transmission of H.264/AVC video bit stream through CBR(Constant Bit Rate) channel is proposed. The proposed algorithm predicts an adaptive QP(Quantization Parameter) for improving video distortion, due to high motion and abruptly scene change, which target bit rate and MAD(Mean of Absolute Difference) for current frame considering image complexity variance between previous and current frames. Additionally, it uses frame skip technique to maintain bit stream within a manageable range and protect buffer from overflow or underflow. Experimental results show that the proposed method gives a quality improvement of about 0.5dB when compared to previous rate control algorithm. Also our proposed algorithm encodes the video sequences with less frame skipping compared to the existing rate control for H.264/AVC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.95-104
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• 2004

This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.55-65
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• 2006

Most of fast block motion estimation algorithms reported so far in literatures aim to reduce the computation in terms of the number of search points, thus do not fit well with multimedia processors due to their irregular data flow. For multimedia processors, proper reuse of data is more important than reducing number of absolute difference operations because the execution cycle performance strongly depends on the number of off-chip memory access. Therefore, in this paper, we propose a Hexagon-shape line search (HEXSLS) algorithm using line search pattern which can increase data reuse from on-chip local buffer, and check sub-sampling points in line search pattern to reduce unnecessary SAD operation. Our experimental results show that the prediction error (MAE) performance of the proposed HEXSLS is similar to that of the full search block matching algorithm (FSBMA), while compared with the hexagon-based search (HEXBS), the HEXSLS outperforms. Also the proposed HEXSLS requires much lesser off-chip memory access than the conventional fast motion estimation algorithm such as the hexagon-based search (HEXBS) and the predictive line search (PLS). As a result, the proposed HEXSLS algorithm requires smaller number of execution cycles on media processor.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.2
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• pp.89-98
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• 2009

In the field of computer vision, image mosaicking is a common method for effectively increasing restricted the field of view of a camera by combining a set of separate images into a single seamless image. Image mosaicking based on feature points has recently been a focus of research because of simple estimation for geometric transformation regardless distortions and differences of intensity generating by motion of a camera in consecutive images. Yet, since most feature-point matching algorithms extract feature points using gray values, identifying corresponding points becomes difficult in the case of changing illumination and images with a similar intensity. Accordingly, to solve these problems, this paper proposes a method of image mosaicking based on feature points using color information of images. Essentially, the digital values acquired from a digital color camera are converted to values of a virtual camera with distinct narrow bands. Values based on the surface reflectance and invariant to the chromaticity of various illuminations are then derived from the virtual camera values and defined as color-invariant values invariant to changing illuminations. The validity of these color-invariant values is verified in a test using a Macbeth Color-Checker under simulated illuminations. The test also compares the proposed method using the color-invariant values with the conventional SIFT algorithm. The accuracy of the matching between the feature points extracted using the proposed method is increased, while image mosaicking using color information is also achieved.

• Journal of the Korean BIBLIA Society for library and Information Science
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• v.13 no.1
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• pp.167-182
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• 2002

Rapidly changing information technologies and changes in new information type provide a new turning point in librarian's role and job as an information specialist. A library traditionally processes and manages paper-type information resources. But, with new requirements to library and changes of information sources, a digital library for use, management, and delivery of information came into existence. The appearance of digital library provides new direction for information processing and requires various changes in roles of information specialists for appropriately and quickly providing information and knowledge for users. The developments of information technology related to information and knowledge and environmental changes around library provide information specialist, who have a role in information processing and delivery, with new challenging areas. On the other hand, the traditional library areas can be infringed upon by those factors. With such rapid changes, an information specialist with a major in library and information science makes various efforts to keep their status as an information specialist and performs their role in information siciety. Currently, they partially lead an active role in the areas relating information and knowledge. This paper focuses on information specialist' current status and role in not library areas but new areas related to information technologies, and figures out requirements to take firm position in those areas.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.106-114
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• 2010

We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.6
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• pp.34-51
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• 2008

Today, the Internet is a part of our life. For that reason, we regard revealing characteristics of Internet traffic as an important research theme. However, Internet traffic cannot be easily manipulated because it usually occupy huge capacity. This problem is a serious obstacle to analyze Internet traffic. Many researchers use various sampling techniques to reduce capacity of Internet traffic. In this paper, we compare several famous sampling techniques, and propose efficient sampling scheme. We chose some sampling techniques such as Systematic Sampling, Simple Random Sampling and Stratified Sampling with some sampling intensities such as 1/10, 1/100 and 1/1000. Our observation focused on Traffic Volume, Entropy Analysis and Packet Size Analysis. Both the simple random sampling and the count-based systematic sampling is proper to general case. On the other hand, time-based systematic sampling exhibits relatively bad results. The stratified sampling on Transport Layer Protocols, e.g.. TCP, UDP and so on, shows superior results. Our analysis results suggest that efficient sampling techniques satisfactorily maintain variation of traffic stream according to time change. The entropy analysis endures various sampling techniques well and fits detecting anomalous traffic. We found that a traffic volume diminishment caused by bottleneck could induce wrong results on the entropy analysis. We discovered that Packet Size Distribution perfectly tolerate any packet sampling techniques and intensities.