• Title/Summary/Keyword: 전자빔 묘화

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전자빔을 이용한 미세형상 패턴성형용 S/W의 개발

  • 강재훈;송준엽;이승우;박화영
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2004.05a
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    • pp.243-243
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    • 2004
  • 상용화된 주사식 전자현미경(SEM)을 기본 구조로 하는 가공 시스템을 구축하여 전자빔(Electron beam)을 이용한 초미세 패턴(Nano pattern) 등 형상의 직접 성형, 혹은 직접 묘화(Direct writing) 가공을 수행하기 위해서는 크게 분류하여 연속적으로 스캐닝되는 전자빔을 요구에 따라 적절하게 극히 짧은 시간 내에 개폐하는 빔 블랭커(Beam blanker)와 효율적으로 초미세 패턴 등의 형상을 설계ㆍ가공하기 위한 전용 S/W의 두 가지 요소가 반드시 적용되어야 한다.(중략)

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Nano-scale pattern delineation by fabrication of electron-optical lens for micro E-beam system (마이크로 전자빔 시스템을 위한 전자광학렌즈의 제작에 의한 나노 패턴 형성)

  • Lee, Yong-Jae;Park, Jung-Yeong;Chun, Kuk-Jin;Kuk, Young
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.9
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    • pp.42-47
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    • 1998
  • We have fabricated electron-optical lens for micro E-beam system that can overcome the limitation of current E-beam lithography. Our electron-optical lens consists of multiple silicon electrodes which were fabricated by micromachining technology and assembled by anodic bonding. The assembled system was installed in UHV chamber to observe the emission characteristics of focused electrons by the electro-optical lens. We used STM(Scanning Tunneling Microscope) tip for electron source. By performing lithography with the focused electrons with PMMA(poly-methylmethacrylate) as E-beam resist. We could draw 0.13${\mu}{\textrm}{m}$ nano-scale lines.

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Fabrication of the grating array using computer generated phase mask (Computer generated phase mask를 이용한 격자 array 제작)

  • 원형식;김상인;박선택;송석호;오차환;김필수
    • Proceedings of the Optical Society of Korea Conference
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    • 2001.02a
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    • pp.158-159
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    • 2001
  • 파장분할다중 방식에서 필요로 하는 격자들 간의 격자주기 차이는 1nm이하를 요구한다. 따라서, 하나의 위상형 마스크로 서로 다른 주기의 격자를 동시에 제작하려면 하나의 위상형 마스크 패턴들 간에도 nm 정도의 차이를 갖는 미세한 패턴이 있어야 한다. 그러나, 일반적으로 마스크를 제작하는데 이용되는 장비인 전자빔 묘화장치(electron-beam lithographic system)의 분해능은 수십 nm이므로, 그러한 nm 정도의 정확도로서 조합된 마스크 패턴들을 만드는 것은 매우 어렵다. (중략)

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Submicron Patterning in Electron Beam Lithography using Trilayer Resist (삼층감광막구조를 이용한 미세패턴의 전자빔 묘화)

  • 배용철;서태원;전국진
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.10
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    • pp.101-107
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    • 1994
  • The PMMA/Ge/AZ trilayer resist decreased proximity effect of backscattering electrons and corrected pattern distoration in order to from deep submicron patterns. In the experiment, the prosiemity effect is decreased by 11% and 30% for the case of 0.9$\mu$m and 1.7$\mu$m AZ, respectively, in trilayer resist compared to monolyer resist. also, the EID of 240$\AA$ Ge film is smaller than that of 500$\AA$ film by 365. 0.1$\mu$m line/space was formed in the 2000$\AA$ PMMA layer with the condition of dose 330${\mu}C/cm^{2}$ and of 150sec of develop time in MIBK : IPA (1:3) developer.

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Fabrication technology of the focusing grating coupler using single-step electron beam lithography (Single-step 전자빔 묘화 장치를 이용한 Focusing Grating Coupler 제작 연구)

  • Kim, Tae-Youb;Kim, Yark-Yeon;Sohn, Yeung-Joon;Han, Gee-Pyeong;Paek, Mun-Cheol;Kim, Hae-Sung;Shin, Dong-Hoon;Rhee, Jin-Koo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07b
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    • pp.976-979
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    • 2002
  • A focusing grating coupler (FGC) was not fabricated by the 'Continuous Path Control' writing strategy but by an electron-beam lithography system of more general exposure mode, which matches not only the address grid with the grating period but also an integer multiple of the address grid resolution (5 nm), To more simplify the fabrication, we are able to reduce a process step without large decrease of pattern quality by excluding a conducting material or layer such as metal (Al, Cr, Au), which are deposited on top or bottom of an e-beam resist to prevent charge build-up during e-beam exposure. A grating pitch period and an aperture feature size of the FGC designed and fabricated by e-beam lithography and reactive ion etching were ranged over 384.3 nm to 448.2 nm, and $0.5{\times}0.5mm^2$ area, respectively, This fabrication method presented will reduce processing time and improve the grating quality by means of a consideration of the address grid resolpution, grating direction, pitch size and shapes when exposing. Here our investigations concentrate on the design and efficient fabrication results of the FGC for coupling from slab waveguide to a spot in free space.

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Direct Patterning Technology of Indium Tin Oxide Layer using Nd:$YVO_4$ Laser Beam (Nd:$YVO_4$ 레이저 빔을 이용한 인듐 주석 산화물 직접 묘화 기술)

  • Kim, Kwang-Ho;Kwon, Sang-Jik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.11
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    • pp.8-12
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    • 2008
  • For the reduction of fabrication cost and process time of AC plasma display panel (PDP), indium tin oxide (ITO) layer was patterned as bus electrode using Nd:$YVO_4$ laser. In comparison with the chemically wet etched ITO patterns, laser ablated ITO patterns showed the formation of shoulders and ripple-like structures at the edge of the ITO lines. For the reduction of shoulders and ripple-like structures, pulse repetition rate and scan velocity of laser was changed. In addition, we analyzed a discharge characteristic of PDP test panel to observe how the shoulders and ripple-like structures influence on the PDP. Based on experimental results, the pattern etched at the 500 mm/s and 40 kHz was better than any other condition. From this experiment we could see the possibility of the laser direct patterning for the application to the patterning of ITO in AC-PDP.

Studies on the Fabrication of 0.2 ${\mu}m$Wide-Head T-Gate PHEMT′s (0.2 ${\mu}m$ Wide-Head T-Gate PHEMT 제작에 관한 연구)

  • Jeon, Byeong-Cheol;Yun, Yong-Sun;Park, Hyeon-Chang;Park, Hyeong-Mu;Lee, Jin-Gu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.1
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    • pp.18-24
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    • 2002
  • n this paper, we have fabricated pseudomorphic high electron mobility transistors (PHEMT) with a 0.2 ${\mu}{\textrm}{m}$ wide-head T-shaped gate using electron beam lithography by a dose split method. To make the T-shape gate with gate length of 0.2 ${\mu}{\textrm}{m}$ and gate head size of 1.3 ${\mu}{\textrm}{m}$ we have used triple layer resist structure of PMMA/P(MMA-MAA)/PMMA. The DC characteristics of PHEMT, which has 0.2 ${\mu}{\textrm}{m}$ of gate length, 80 ${\mu}{\textrm}{m}$ of unit gate width and 4 gate fingers, are drain current density of 323 ㎃/mm and maximum transconductance 232 mS/mm at $V_{gs}$ = -1.2V and $V_{ds}$ = 3V. The RF characteristics of the same device are 2.91㏈ of S21 gain and 11.42㏈ of MAG at 40GHz. The current gain cut-off frequency is 63GHz and maximum oscillation frequency is 150GHz, respectively.ively.