• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of IKEEE
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• v.24 no.3
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• pp.859-866
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• 2020

This paper proposes a 2-ch DC-DC converter with a wide-input voltage range from 2.9V~5.6V for wearable AMOLED displays. For positive voltage V_POS, a boost converter is designed using an over-charged voltage permissible circuit (OPC) which generates a normal output voltage even if over-input voltage is applied, and a SPWM-PWM dual mode with 3-segmented power transistors to improve efficiency at light load. For negative voltage V_NEG, a 0.5x regulated inverting charge pump is designed to increase power efficiency. The proposed DC-DC converter was designed using a 0.18-㎛ BCDMOS process. Simulation results show that the proposed DC-DC converter generates V_POS voltages of 4.6 V and V_NEG voltage of -0.6V~-2.3V for input voltage of 2.9V to 5.6V. In addition, it has power efficiency of 49%~92%, output ripple voltage has less than 20 mV for load current range of 1 mA~70 mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.

• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.288-295
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• 2009

We report the etch characteristics of GaAs and AlGaAs in the diffusion pump-based capacitively coupled $BCl_3$ plasma. Process variables were chamber pressure ($50{\sim}180$ mTorr), CCP power ($50{\sim}200\;W$) and $BCl_3$ gas flow rate ($2.5{\sim}10$ sccm). Surface profilometry was used for etch rate and surface roughness measurement after etching. Scanning electron microscopy was used to analyze the etched sidewall and surface morphology. Optical emission spectroscopy was used in order to characterize the emission peaks of the $BCl_3$ plasma during etching. We have achieved $0.25{\mu}m$/min of GaAs etch rate with only 5 sccm $BCl_3$ flow rate when the chamber pressure was in the range of 50{\sim}130 mTorr. The etch rates of AlGaAs were a little lower than those of GaAs at the conditions. However, the etch rates of GaAs and AlGaAs decreased significantly when the chamber pressure increased to 180 mTorr. GaAs and AlGaAs were not etched with 50 W CCP power. With $100{\sim}200\;W$ CCP power, etch rates of the materials increased over $0.3{\mu}m$/min. It was found that the etch rates of GaAs and AlGaAs were not always proportional to the increase of CCP power. We also found the interesting result that AlGaAs did not etched at 2.5 sccm $BCl_3$ flow rate at 75 mTorr and 100 W CCP power even though it was etched fast like GaAs with more $BCl_3$ gas flow rates. By contrast, GaAs was etched at ${{\sim}}0.3{\mu}m$/min at the 2.5 sccm $BCl_3$ flow rate condition. A broad molecular peak was noticed in the range of $500{\sim}700\;mm$ wavelength during the $BCl_3$ plasma etching. SEM photos showed that 10 sccm $BCl_3$ plama produced more undercutting on GaAs sidewall than 5 sccm $BCl_3$ plasma.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.3
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• pp.465-470
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• 2017

This paper designs and implements a smart garden system using probabilistic filter algorithm using SLAM that can be used in apartment or veranda. To do this, we used Arduino and environtal sensors, which are open hardware controllers, and designed to control and observe automatic water supply, lighting, and growth monitoring with three wireless systems (Bluetooth, Ethernet, WiFi). This system has been developed to make it possible to use it in an indoor space such as an apartment, rather than a large-scale cultivation system such as a conventional plant factory which has already been widely used. The developed system collects environmental data by using soil sensor, illuminance sensor, humidity sensor and temperature sensor as well as control through smartphone app, analyzes the collected data, and controls water pump, LED lamp, air ventilation fan and so on. As a wireless remote control method, we implemented Bluetooth, Ethernet and WiFi. Finally, it is designed for users to enable remote control and monitoring when the user is not in the house.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• Journal of Drive and Control
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• v.16 no.4
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• pp.1-8
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• 2019

The HPM (High-speed Power Matching) system is an electro-hydraulic control system. It directly controls the swash plate of the pump by selecting four-loop logic based on joystick signals, pump flow, and pressure signal to improve the efficiency and controllability of construction machines. In the NFC (Negative Flow Control) system, a typical pump control system using conventional open center type MCV, the loss is continuously generated by flow through the center bypass line even when the excavator is not in operation. Also, due to the slow response of the pump that indirectly controls the flow rate using the pressure regulator, peak pressure occurs at the start or stop of the operation. Conversely, the HPM system uses an MCV without center-by-pass flow path and the swash plate of a pump for the HPM is controlled by a high-speed proportional flow control valve. As a result, the HPM system minimizes energy loss in standby state of the excavator and enables peak pressure control through rapid electro-hydraulic control of a pump. In this paper, the concept of the HPM system algorithm is introduced and the hydraulic system efficiency is compared with the NFC system using the excavator SAT (System Analysis Tool).

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.26 no.5
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• pp.567-577
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• 2016

The hutches which are installed in the beamline are largely classified into two, i.e XPP (X-ray pump probe) and CXI (Coherent X-ray image). Laser room is installed on the hutch and provides laser to XPP and CXI simultaneously. And two hutches have heavy crane to install some optics equipments. Safety and reliability of hutch structures should be taken into account for the precise operating of the laser facilities, so vibration analysis is essential to do this. The main purpose of vibration analysis is to install hutch structures with large stiffness. We have changed materials specification several times to install hutch structures having strong stiffness. Now hutch structures were installed and checked vibration status at laser room and XPP hutch. The results of laser table and robot arm satisfy vibration criteria. This paper explains about the design and vibration analysis of hutch structures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.3
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• pp.454-462
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• 1998

Mechanisms and conditions for rounding of AUC particles were examined during AUC precipitation. Rounding of AUC particle was possible only by external circulation using pump, not by internal circulation using agitator. The rate of AUC rounding $(dn_p/dt)$ was proporational to operation conditions such as magma density $(M_t:g-U/{\iota}l)$, turn over ratio $(T_o)$ and impeller tip velocity of pump (U); $ dn_p/dt{\propto}M_t{\cdot}T_o{\cdot}U^2$. The validity of this relationship was qualitatively confirmed by comparing the expermental results. Two rounding mechanisms were suggested. One is crack formation mechanism and the other etch-pit formation mechanism on the surface of AUC particle. It was found that the crack formation is more dominant at the initial stage and the etch-pit formation at the final stage of the AUC precipitation.