• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.1
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• pp.153-162
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• 2018

The importance of energy harvesting technique is increasing due to the elevated level of demand for sustainable power sources for wearable device applications. In this study, we developed an Energy Harvesting wearable Platform(EH-P) architecture which is used in the design of a multi-energy source based on TENG. The proposed switching circuit produces power with higher current at lower voltage from energy harvesting sources with lower current at higher voltage. This can powers microcontrollers for a short period of time by using PV and TENG complementarily placed under hard conditions for the sources such as indoors. As a result, the whole interface circuit is completely self-powered with this makes it possible to run of sensing on a Wearable device platform. It was possible to increase the wearable device life time by supplying more than 29% of the power consumption to wearable devices. The results presented in this paper show the potential of multi-energy harvesting platform for use in wearable harvesting applications, provide a means of choosing the energy harvesting source.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.105-113
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• 2008

While the wireless sensor network has a strong point which does not have effect on whole activities of network even though neighboring sensor nods fail activities of some sensor nod or make some functions disappear by the characteristic of similar information detection, it has problems which is slowing down of wireless medium, transfer character with severe error, limited power supply, the impossibility of change by optional arrangement of sensor nods etc. This paper proposes PRML techniques which performs the fittest course searching process to reduce power consumption of entire nods while guarantees the scalability of network organizing sensor nods hierarchically. The proposed technique can scatter the load of cluster head by considering the connectivity with surplus energy of nod and reduce the frequency of communication among the nods. As a result of the analysis in comparison with LEACH-C and HEED technique, PRML technique get efficiency of average 6.4% in energy consuming respect of cluster head, efficiency of average 8% in entire energy consuming respect, and more efficiency of average 7.5% in other energy consuming distribution of network scalability than LEACH-C and HEED technique.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• Bulletin of the Korean Space Science Society
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• 2009.10a
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• pp.45.1-45.1
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• 2009

과학기술위성 3호의 주탑재체인 MIRIS (Multi-purpose InfraRed Imaging System)는 우주관측카메라 (Space Observation Camera, SOC)와 지구관측카메라 (Earth Observation Camera, EOC)가 독립적인 시스템으로 구성되어 있다. 지구관측카메라는 유효 구경 100 mm, F/5의 광학계로 3-5 마이크론 파장영역을 관측하며, 국내에서 개발된 적외선 검출기의 우주 인증 시험과 유사시 한반도 적외선 감시를 주요 목적으로 하고 있다. 고도 700km에서 지상을 볼 때 약 42m/pixel의 공간분해능을 나타낼 것으로 기대하고 있다. 지구관측카메라의 인증 모델(Qualification Model)은 냉동기를 제외한 모든 부품이 국내기술로 제작되었으며, 미러 본딩 및 릴레이 렌즈 조립 기술, 적외선 영상 검교정 기술 등 다양한 경험과 도전을 제공했다. 이 발표에서는 지구관측카메라 인증모델을 이용하여 수행한 주요 시험 과정을 소개한다. 국내 회사 (주)i3 system에서 제작된 적외선 검출기는 $320\times256$ HgCdTe array (평균 양자효율 80% 이상) 이며 77K에서 정상적으로 운영된다. Micro Stirling Cooler에 의해 듀어는 전원을 켠 후 5분 이내에 검출기 운영온도인 77K까지 내려간다. 적외선 광학계의 정렬, 시스템 MTF 측정, 흑체 측정 및 검교정 작업을 수행한 후 야외에서 다양한 경우에 대해 Field Test를 진행했다. 이 발표에서는 Field Test 과정과 이를 통해 얻은 결과를 발표하고, FM (Flight Model) 제작에 있어 수정해야 할 사항들을 제안해 본다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.51-57
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• 2020

WSN is a wirelessly configured network of sensor nodes with limited power such as batteries. If the sensor node's battery is exhausted, the node is no longer available. Therefore, if the network is to be used for a long time, energy consumption should be minimized. There are many Wireless Sensor Network Protocols to improve energy efficiency, including Cluster-based and chain-based Protocols. This paper seeks to examine the performance evaluation of routing protocols studied separately for the improvement of performance in wireless sensor network. The criteria for comparison were selected as the LEACH protocol, a representative hierarchical routing protocol, and the comparison targets considered CHEF and FLCFP and LEACH-DFL routing protocols with Fuzzy Logic. Various criteria for performance comparison were presented in this paper, and the performance was compared through simulation of each protocol. The purpose is to present a reference point for comparing the performance of other protocols through the performance comparison of CHEF, FLCFP, and LEACH-DFL, protocols with LEACH and Fuzzy Logic, and to provide additional design methods for improving the performance of protocols.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.6
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• pp.71-78
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• 2002

A method of soft switching in the half bridge converter using a small saturable core is presented. For the soft switching, a small dead time of both switch off is made in a pair of MOSFET switch. The saturable core is of rectangular magnetization characteristics and the core flux swings from the minus to the plus saturation during ON time of the switch. The soft switching is realized in dead time by a resonance between the saturating inductance of the core and the stray capacitance of MOSFET. As an extension of this concept, instead of the saturable core, we propose a new soft switching circuit using a linear inductance and two switches, which is especially suitable for regulating the output and also for high frequency switching. A theoretical principle of soft switching presented here was confirmed by experiments on a half bridge converter of 1.25 KW.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.1
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• pp.26-45
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• 2001

The Flash memory market: is an exciting market that has quickly over the last 10 years. Recently Flash memory provides a high-density. truly non-volatile, high performance read write memory solutions, also is characterized by low power consumption, extreme ruggedness and high reliability. Flash memory is an optimum solution for large nonvolitilc storage operations such as solid file storage, digital video recorder, digital still camera, The MP3 player and other portable multimedia communication applications requiring non-volatility. Regardless of the type of Flash memory, Flash media management software is always required to manage the larger Flash memory block partitions. This is true, since Flash memory cannot be erased on the byte level common to memory, but must be erased on a block granularity. The management of a Flash memory manager requires a keen understanding of a Flash technology and data management methods. Though Flash memory's write performance is relatively slow, the suggested algorithm offers a higher maximum write performance. Algorithms so far developed is not suitable for applications which is requiring more fast and frequent accesses. But, the proposed algorithm is focused on the justifiable operation even in the circumstance of fast and frequent accesses.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.31-36
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• 2011

This paper investigates the ESD robustness of the stacked output driver with a 0.13um CMOS process. To represent an actual I/O system, we implemented stacked output driver circuits with pre-drivers and a rail-based power clamp. We implemented eight kinds of circuits varying pre-driver input connections and stacked driver size. The test circuits are examined with TLP measurements. It is shown that breakdown current and voltage can be increased by connecting the pre-driver input to a power supply and using stacked devices of a similar size. Based on the test results, design guideline is suggested to improve ESD robustness of the stacked output drivers.