• Title/Summary/Keyword: 전원전압레벨 검출

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Design of the Embedded EPROM Circuits Aiming at Low Voltage Operation (저 전압동작을 위한 내장형 EPROM회로설계)

  • 최상신;김성식;조경록
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.6
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    • pp.421-430
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    • 2003
  • In the embedded system, EPROM is difficult to replace a mask ROM for the applications using battery, because the low voltage characteristic of an EPROM is inferior to that of a mask ROM. In this paper, the new circuits such as a word line voltage hoosier scheme and a sense amplifier without reference input for an embedded EPROM in MCU are proposed. The circuits can detect bit line voltage a predetermined level, which is caused by the degradation of the battery. We fabricated a MCU embedded 32Kbytes EPROM. The proposed circuits well operated at 1.5V supply voltage and thus the low voltage performance was improved by about 30%.

A Design of Transceiver for 13.56MHz RFID Reader using the Peak Detector with Automatic Reference Voltage Generator (자동 기준전압 생성 피크 검출기를 이용한 13.56 MHz RFID 리더기용 송수신기 설계)

  • Kim, Ju-Seong;Min, Kyung-Jik;Nam, Chul;Hurh, Djyoung;Lee, Kang-Yun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.3
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    • pp.28-34
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    • 2010
  • In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA(Variable Gain Amplifier), filter, comparator to recovery the received signal. The proposed automatic reference voltage generator, positive peak detector, negative peak detector, and data slicer circuit can adjust the decision level of reference voltage over the received signal amplitudes. The transmitter is designed to drive high voltage and current to meet the 15693 specification. By using inductor loading circuit which can swing more than power supply and drive large current even under low impedance condition, it can control modulation rate from 30 percent to 5 percent, 100 perccnt and drive the output currents from 5 mA to 240 mA depending on standards. The 13.56 MHZ RFID reader is implemented in $0.18\;{\mu}m$ CM08 technology at 3.3V single supply. The chip area excluding pads is $1.5mm\;{\times}\;1.5mm$.

Multi-Channel Analog Front-End for Auditory Nerve Signal Detection (청각신경신호 검출 장치용 다중채널 아나로그 프론트엔드)

  • Cheon, Ji-Min;Lim, Seung-Hyun;Lee, Dong-Myung;Chang, Eun-Soo;Han, Gun-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.1
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    • pp.60-68
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    • 2010
  • In case of sensorineural hearing loss, auditory perception can be activated by electrical stimulation of the nervous system via electrode implanted into the cochlea or auditory nerve. Since the tonotopic map of the human auditory nerve has not been definitively identified, the recording of auditory nerve signal with microelectrode is desirable for determining the tonotopic map. This paper proposes the multi-channel analog front-end for auditory nerve signal detection. A channel of the proposed analog front-end consists of an AC coupling circuit, a low-power 4th-order Gm-C LPF, and a single-slope ADC. The AC coupling circuit transfers only AC signal while it blocks DC signal level. Considering the bandwidth of the auditory signal, the Gm-C LPF is designed with OTAs adopting floating-gate technique. For the channel-parallel ADC structure, the single-slope ADC is used because it occupies the small silicon area. Experimental results shows that the AC coupling circuit and LPF have the bandwidth of 100 Hz - 6.95 kHz and the ADC has the effective resolution of 7.7 bits. The power consumption per a channel is $12\;{\mu}W$, the power supply is 3.0 V, and the core area is $2.6\;mm\;{\times}\;3.7\;mm$. The proposed analog front-end was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.