• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.2
• /
• pp.208-217
• /
• 2010

This paper presents a novel 10 GHz bio-radar system based on a frequency multiplier and phase-locked loop(PLL) for non-contact measurement of heartbeat and respiration rates. In this paper, a 2.5 GHz voltage controlled oscillator (VCO) with PLL is employed to as a frequency synthesizer, and 10 GHz continuous wave(CW) signal is generated by using frequency multiplier from 2.5 GHz signal. This paper also presents the noise characteristic of the proposed system. As a result, a better performance and economical frequency synthesizer can be achieved with the proposed bio-radar system. The experimental results shows excellent bio-signal measurement up to 100 cm without any additional digital signal processing(DSP), and the proposed system is validated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.12
• /
• pp.941-947
• /
• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.3
• /
• pp.485-490
• /
• 2012

In this paper, driver circuit of LED lights for ships is designed and implemented to replace conventional lights with filament which have short life time due to vibration of ships. The driver of LED module is switching circuit without transformer to reduce volume and cost. As switch circuit controls input 220 VAC with PWM, LED module is reliably driven. Power factor is improved by using valley-fill PFC compensation circuit which is handled to pulse current of switching circuit. Serial-parallel LED circuit is applied to reduce change period of lights of long-term navigation ships. Array of serial-parallel can operate even if some of LEDs is damaged. It is suitable for ships that power consumption and power factor of lights including developed drive circuit have 39Watt and 0.925 respectively.

• Journal of the Korean Electrochemical Society
• /
• v.15 no.3
• /
• pp.115-123
• /
• 2012

As the market of lithium secondary batteries moves from mobile IT devices to large-format electric vehicles or energy storage systems, the strengthened battery specifications such as long-term reliability longer than 10 years, pack-level safety and tough competitive price have been required. Moreover, even though high power properties should also be achieved for hybrid electric vehicles, it is not easy to measure accurate power values at various conditions. Because it is difficult to choose a proper measurement method and its experimental condition is more complex comparing to capacity measurement. In addition, the power values are very sensitive to power duration time, state-of-charge (SOC) of cells, cut-off voltages, and temperatures, whereas capacity values are not. In this paper, we introduce three kinds of power measurement methods, hybrid pulse power characterization (HPPC) suggested by US FreedomCar, so-called J-pulse by Japan electric vehicle association standards (JEVS) and constant power measurement, respectively. Moreover, with pouch-type unit cells for HEV, experimental power data are discussed in order to compare each power measurement.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.14 no.2
• /
• pp.89-95
• /
• 2009

Tracking the Maximum Power Point(MPP) of a photovoltaic(PV) array is usually an essential part of a PV system. The problem considered by MPPT techniques is to find the voltage $V_{MPP}$ or current $I_{MPP}$ at which a PV array should operate to generate the maximum power output PMPP under a given temperature and irradiance. The MPPT control methods, such as the perturb and observe method and the incremental conductance method require microprocessor or DSP to determine if the duty cycle should be increased or not. This paper proposes a simple and fast analog MPPT method. The proposed control scheme will track the MPP very fast and its hardware implementation is so simple, compared with the conventional techniques. The new algorithm has successfully tracked the MPP, even in case of rapidly changing atmospheric conditions, and Has higher efficiency than ordinary algorithms.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.65 no.1
• /
• pp.23-30
• /
• 2016

Wake effects cause wind turbine generators (WTGs) within a wind power plant (WPP) to produce different levels of active power and subsequent reactive power capabilities. Further, the impedance between a WTG and the point of interconnection (POI)-which depends on the distance between them-impacts the WPP's reactive power injection capability at the POI. This paper proposes a voltage control scheme for a WPP based on the available reactive current of the doubly-fed induction generators (DFIGs) and its impacts on the POI to improve the reactive power injection capability of the WPP. In this paper, a design strategy for modifying the gain of DFIG controller is suggested and the comprehensive properties of these control gains are investigated. In the proposed scheme, the WPP controller, which operates in a voltage control mode, sends the command signal to the DFIGs based on the voltage difference at the POI. The DFIG controllers, which operate in a voltage control mode, employ a proportional controller with a limiter. The gain of the proportional controller is adjusted depending on the available reactive current of the DFIG and the series impedance between the DFIG and the POI. The performance of the proposed scheme is validated for various disturbances such as a reactive load connection and grid fault using an EMTP-RV simulator. Simulation results demonstrate that the proposed scheme promptly recovers the POI voltage by injecting more reactive power after a disturbance than the conventional scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.3
• /
• pp.1-7
• /
• 2012

A 9b MS/s CMOS cyclic folding A/D converter (ADC) for intelligent battery sensor and battery management systems is proposed. The proposed ADC structure is based on a cyclic architecture to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolating structure. The prototype ADC implemented with a 0.35um 2P4M n-well CMOS process shows a measured INL and DNL of maximum 1.5LSB and 1.0LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 48dB and 60dB, respectively, and the power consumption is about 110mW at 2MS/s and 3.3V. The occupied active die area is $10mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.7
• /
• pp.17-22
• /
• 2008

This paper presents a low-power and small-area pulse width modulator by light intensity for photoflash. Light intensity controller is achieved by using capacitor, photodiode, and comparator. The proposed circuit designs digital circuit to reduce static power consumption except comparator. And IGBT driver has short circuit protection using delay cell. The pulse width modulator has the operating range of $V_{MS}$ from 0.5V to 2.5V and pulse width of output from 0.14ms to 1.65ms at 300Hz. The pulse width modulator fabricated in $0.35-{\mu}m$ CMOS technology occupies $0.85mm{\times}0.56mm$. This circuit consumes 3.0mW at 300Hz and 3.0V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.7
• /
• pp.63-70
• /
• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.11
• /
• pp.1248-1258
• /
• 2010

In this paper, a method for simultaneously realizing the sum and difference patterns which are required in the monopulse radar sensor systems, is presented by using single taper array antenna with rectangular microstrip patches. The widths of patches are first determined by the voltage weights which are synthesized for the fundamental array factor patterns to be applied to the monopulse operation by using the sidelobe levels(SLLs) control technique. As the bi-directionally series-fed technique is applied and the lengths of connecting lines between patches are appropriately adjusted, the single array generates two phase-shifted beams which activates out-of-phase and in-phase ports of a $180^{\circ}$ hybrid coupler to synthesize the sum and difference patterns. The simulated results on the configuration designed at 9.5 GHz are compared with measured results showing the validity of the proposed method.