• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1415-1417
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• 2003

Yoneyama 등이 2001년 기존의 potentiometry 형의 요소 센서보다 우수한 성능을 갖는ampeometry 정의 요소 센서를 제안한 이후, 전자 전달 메커니즘에 관한 관심이 집중되어 왔으나, urease로부터 전극 기질까지의 전자 전달 매질로서 전도성 고분자보다 쉽고 단순한 공정은 아직까지 제시된 바 없다. 본 논문에서는 전도성 고분자로서 polypyrrole(PPy)과 poly(3-methylthiophene)(P3MT)을 이용하여 다공성 실리콘(PS) 요소 센서를 제작하고 각각의 특성을 전기화학적으로 분석하였다. Urease 고정화 전압, 고정화 시간, 고정화 시의 효소 농도, 수소이온 농도 등이 감도에 미치는 영향은 PPy 와 P3MT 각각의 경우 유사한 경향성을 보였다. 감도 특성의 경우, PPy는 다공질 실리콘 전극과 평면 전극 각각에 대하여 1.55 ${\mu}A/mM{\cdot}cm^2$와 0.91 ${\mu}A/mM{\cdot}cm^2$였고, P3MT의 경우는 각각 8.44 ${\mu}A/mM{\cdot}cm^2$와 4.28 ${\mu}A/mM{\cdot}cm^2$의 감도를 보였다. 즉, PPy가 P3MT 보다 일반적으로 높은 감도를 보였고, 다공질 실리콘 전극을 사용하는 경우, 그렇지 않은 경우보다 약 2배외 감도 향상 효과를 기대할 수 있었다. 재현성이나 안정성의 경우는 P3MT 가 PPy 보다 우수하였다. 사용 빈도에 따른 감도 저하는 다공질 실리콘 전극의 경우 직선적으로 감소하셨으나 평면 전극의 경우는 지수함수적으로 감소하였다 시간에 따른 감도 저하 현상은 만15일 이후의 감도를 기준으로 하여, 10% 미만의 감도저하를 보임으로써 PPy, P3MT 모두 우수한 특성을 보였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.5
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• pp.29-34
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• 1977

Using JFET and bipolar transistor, we have designed a circuit of current controlled negative resitance and analysed this circuit in the operating region. Since the positive gate voltage of N-channel JFET is applied in full operating region, the output and transfer characteristics of JFET are measured in the positive gate region. The performances of this circuit are predicted from these characteristics and experimental results of the proposed CCNR circuit are presented.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.6
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• pp.14-20
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• 1975

Characteristics of coupled trigonometric transmission lines (CTTL) are studies based on the theory of general coupled nonuniform transmission lines. First, the 4-port transmission matrix parameters of networks and directional couplers using CTTL. The phase slrift characteristic of the all-pass networks and the magnitude characteristic of the directional couplers are studied in detail for various coupling and a high-pass small ripple directional coupler using CTTL are given and their physical realization is considered.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.5
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• pp.72-79
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• 2009

Solar energy is desirable due to its renewable and pollution-free properties. In order to utilize the present utility grid infrastructure for power transmission and distribution, a do-dc boost converter and grid connected dc-to-ac inverters are needed for solar power generation. The dc-dc boost converter allows the PV system to operate at high do-link voltage. The single-phase inverter provides the necessary voltage and frequency for interconnection to the grid. In this paper, first, current loop transfer function of a single-phase grid-tie inverter has been systematically derived Second the MPPT of conductance increment method at converter side is proposed to supply the maximum power to the inverter side. Simulation results are shown to access the performance of PV system and its behaviour at the interconnection point.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.1
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• pp.68-79
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• 1992

In the high speed analog system satellite communication system, video signal processing and optical fiber interface circuits, GaAs high gain operational amplifier is advantageous due to obtain a high gain because of its low transconductance and other drawbacks, such as low frequency dispersion and process variation. Therefore in this paper, a circuit techniques for improving the voltage gain for GaAs MESFET amplifier is presented. Also, various types of existing current mirror and current mirror proposed are compared.To obtain the high differential gain, bootstrap gain enhancement technique is used and common mode feedback is employed in differential amplifier.The simulation results show that gain is higher than that of basic amplifier about 18.6dB, and stability and frequency performance of differential amplifier are much improved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.263-268
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• 2003

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (NG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 3V in the main gate 50nm. Also, we know that optimum side gate length for each for main gate length is about 70nm. DG MOSFET shows a small threshold voltage roll-off. From the I-V characteristics, we obtained IDsat=550$mutextrm{A}$/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86.2㎷/decade, transconductance is 114$mutextrm{A}$/${\mu}{\textrm}{m}$ and DIBL (Drain Induced Barrier Lowering) is 43.37㎷. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Then, we have obtained very high cut-off frequency of 41.4GHz in the DG MOSFET.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2009.06a
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• pp.183-184
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• 2009

In this paper the internal or external of the ships mounted electronic devices due to the propagation of electromagnetic interference and to prevent malfunction EMC filter was designed and fabricated. It was designed and fabricated with Ni-Zn ferrite beads of high permeability to make large inductance as the inductor and Feed-through capacitors, which did not have any resonance point, to restraint resonance effectively, and the characteristics was evaluated. The results from the 0 kHz$\sim$1.5 GHz bandwidth of $25{\sim}70$ dB were able to obtain excellent attenuation characteristics. And, when the Electric Fast Transient (EFT) of 4 kV in the level 4 of IEC 61000-4-4 was induced, it was soon attenuated more than 1/6 to 600 V. Therefore, it was confirmed that the developed EMC filter can be used for suppressing ships mounted electromagnetic interference between electronic devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Proceedings of the KIEE Conference
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• 2004.04a
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• pp.169-172
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• 2004

펄스파워 응용기술에 있어서 핵심이 되는 것은 대전력 고반복율의 스위칭 특성을 갖는 스위치 및 구동기술이다. 지금까지 대전력 에너지를 전달하기 위해 사용되고 있는 스위치는 크게 사이라트론 등과 같은 진공 스위치와 자기 스위치, 그리고 반도체 스위치로 구분할 수 있는데 이중에서 기존 반도체 스위치들의 한계를 극복하고 낮은 제작비용으로 대전력 고반복용 펄스 전원 장치 등의 다양한 산업분야에 활용하고자 개발된 반도체 스위치가 바로 RSD (Reverse Switch-on Dynistor)이다. RSD는 애벌런치 전류에 의해 소자 전체를 동시에 턴온시키는 특성이 있으므로 고전압 적용을 위해서 직렬 스택을 구성하는 경우에도 턴온 지연이 거의 없어서 전압 분배기와 같은 추가적인 장치가 필요 없으며 높은 di/dt 특성과 우수한 펄스 통전능력을 가진다. 본 논문에서는 30${\mu}s$의 펄스폭으로 스위칭 할 수 있는 10kV 20kA급 펄스파워용 RSD 스택 시스템의 설계와 실험결과를 보여 주고 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.1-6
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• 2010

We present simulation results on DC characteristics of AlGaN/GaN HEMT having stair-type gate electrodes, in comparison with those of the conventional single gate AlGaN/GaN HEMTs and field-plate enhanced AlGaN/GaN HEMTs. In order to reduce the internal electric field near the gate electrode of conventional HEMT and thereby to increase their DC characteristics, we applied three-layered stacking electrode schemes to the standard AlGaN/GaN HEMT structure. As a result, we found that the internal electric field was decreased by 70% at the same drain bias condition and the transconductance (gm) was improved by 11.4% for the proposed stair-type gate AlGaN/GaN HEMT, compared with those of the conventional single gate and field-plate enhanced AlGaN/GaN HEMTs.