• Title/Summary/Keyword: 전류 신호

Search Result 884, Processing Time 0.027 seconds

Implementation of Arc detection Filter (Arc 검출용 필터의 구현)

  • Lee, Kyu-Min;Back, Won-Hyen;Lee, Hack-Bum;Bang, Sun-Bae;Pack, Chong-Yeon
    • Proceedings of the KIEE Conference
    • /
    • 2011.07a
    • /
    • pp.2146-2147
    • /
    • 2011
  • 전기화재의 원인인 아크 신호는 전류 돌입형, 비선형 및 전류 단속형 부하들의 정상상태와 유사한 전류파형을 갖는다. 이러한 부하들에서 아크를 정확하게 검출하기 위해서는 아크 유무를 정확히 판단 할 수 있는 시스템이 필요하며 이러한 시스템에서 아크검출을 정확히 하는 필터가 중요하다. 본 논문에서는 UL1699의 직렬 아크 발생장치로 아크를 발생시키고 시간 및 주파수 영역에서 아크 전류파형을 분석하였다. 분석결과 아크전류파형은 시간영역에서는 영점전류의 처짐 현상(shoulder)이 발생하고 주파수영역에서는 60Hz의 고조파 성분을 제외한 전대역의 주파수에 걸쳐서 스펙트럼이 증가하였다. 본 논문에서 제시된 아크 검출용 필터는 이러한 특징들 중 주파수 영역의 특징을 검출한다.

  • PDF

A study on the detection method of environment toxic gases by using electrical signal (전기적 신호처리에 의한 환경유해물질 검출연구)

  • Chon, Y.K.;Sun, J.H.;Lee, T.S.
    • Proceedings of the KIEE Conference
    • /
    • 1999.07e
    • /
    • pp.1997-2000
    • /
    • 1999
  • 본 연구에서 제시하는 기공세라믹(Porous Ceramic)에 의한 누설전류 측정법은 기공 사이즈가 일정한 Open Pore Cell내에서 도전성 물질 및 이온화된 물질이 기공 사이에 침투되었을 때 외부에서 전계를 가하므로 써 이들 이온화 된 물질이 chain처럼 배열되어 전기적 병렬회로를 구성시켜 미세한 누설전류를 흐르게 한다. 이 누설전류법에 의한 도전성분 검출을 여러 환경 배출가스에 대한 모의실험을 실시한 결과 기공세라믹인 센서 자체의 누설전류는 가스 온도 150 ($^{\circ}C$) 이상에서 급격한 변화를 보이고 200($^{\circ}C$)에서 센서 자체의 전류치와 가스를 주입하였을 때의 전류치와는 상당한 격차를 두고 변화됨을 알 수 있었다. 그리고 공장연돌이나 자동차 배기관에서 방출되는 가스 중 HC, CO, NO, $CO_2$, $SO_2$, $N_2$ 등에 대한 센서 특성이 각각 달리 나타남을 알 수 있었다.

  • PDF

Analysis on the Voltage, Current and Temperature Signals for Free and Locked Operation of Three Speed Electric Fan (3단 스피드 선풍기 모터의 정상 및 고정 운전에 대한 전압, 전류 및 온도 신호 분석)

  • Kim, Yoon Bok;Kim, Doo Hyun
    • Fire Science and Engineering
    • /
    • v.28 no.3
    • /
    • pp.87-91
    • /
    • 2014
  • This paper is aimed to find electrical fire danger for analyzing the characteristics of temperature, current and voltage signals for motor on electric fan. In order to attain this purpose, detected were the temperature, current and voltage signals on electric wire with free (normal state) and locked (abnormal state) motor. For voltage and current signals, voltage signal is no big difference with normal and abnormal states and current signal is higher in abnormal state (highest 309 mA) than the normal state (highest 203 mA). In the case of Temperature signal, the temperature distribution of the motor as a whole is different. It is difference in the case of the normal state $4^{\circ}C$ and the abnormal state $18^{\circ}C$. In particular, most of the electric wiring to the motor of the fan is attached to the fixture of motor back. Considering at allowable temperature ($60^{\circ}C$) of the electric wire could be accelerated to insulation deterioration. The results of this study will be effectively used in analyzing for electric fire and developing the preventive devices of electric fan.

Monitoring of Machining State in Turning by Means of Information and Feed Motor Current (NC 정보와 이송축 모터 전류를 이용한 선삭 가공 상태 감시)

  • 안중환;김화영
    • Transactions of the Korean Society of Mechanical Engineers
    • /
    • v.16 no.1
    • /
    • pp.156-161
    • /
    • 1992
  • In this research a monitoring system for turning using NC information and the current of feed motor as a monitoring signal was developed. The overall system consists of modules such as learning process, NC data transmission, generation of forecast information, signal acquisition, monitoring and post process. In the learning process, the reference data and the cutting force equation necessary for monitoring are obtained from the accumulated monitoring results. In the generation of forecast information, the information of forecasted cutting forces is acquired from the cutting force equation and NC program and appended to each NC block as a monitor code. Reliability of monitoring is improved by using the monitor code in the real-time monitoring. Monitoring module is divided into two parts : the off-line monitoring where errors of NC program are checked and the on-line monitoring where the level of motor current is monitored during cutting operations. If the actual current level exceeds the limit value provided by the monitor code in the level monitoring, it is recognized as abnormal. In the event of abnormal status, the post processor sends the emergency stop signal to NC controller to stop the operation. Actual experiments have shown that the developed monitoring system works well.

A Charge Pump with Matched Delay Paths for Reduced Timing Mismatch (타이밍 부정합 감소를 위해 정합된 지연경로를 갖는 전하 펌프)

  • Heo, Joo-Il;Heo, Jung;Jeong, Hang-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.49 no.5
    • /
    • pp.37-42
    • /
    • 2012
  • In this paper, a new charge pump is proposed to reduce the timing mismatch in the conventional current-steering charge pumps. Conventional current-steering charge pumps used NMOS input stages both for UP and DOWN signals, which resulted in different numbers of stage for UP and DOWN delay paths. The proposed charge pump has equalized the numbers of stages for UP and DOWN signals by using a PMOS stage for the DOWN signal. The simulation results show that the conventional current-steering charge pump has 14ns and 6ns for optimized timing mismatches between UP and DOWN signals for turn-on and turn-off, respectively. On the other hand, the proposed charge pump has improved timing mismatches of 6ns and 5ns for turn-on and turn-off, respectively. As a result, the reference spurs are reduced from -26dBc to -39dBc for the proposed charge pump. The proposed charge pump was designed by using $0.18{\mu}m$ CMOS technology. The measurement results show that the maximum variation of the charging and discharging current over the charge pump output voltage range of 0.3~1.5V is approximately 1.5%.

Initial Rotor Polarity Detection of Single-phase Permanent Magnet Synchronous Motor Based on Virtual dq-axis (단상 영구자석 동기 전동기의 가상 dq축 기반 초기 회전자 자극 검출)

  • Seo, Sung-Woo;Hwang, Seon-Hwan;Lee, Ki-Chang
    • Journal of IKEEE
    • /
    • v.24 no.4
    • /
    • pp.1004-1010
    • /
    • 2020
  • This paper proposes an initial rotor magnetic pole detection method for single-phase permanent magnet synchronous motors. The target motor cannot obtain position information based on the back emf in the low speed and stop state. Therefore, an open loop starting process is required, and in this process, initial rotor position information for low current and soft start is need. The proposed initial rotor magnetic pole detection algorithm considers the effect of asymmetric air- gap and magnetic flux. In addition, the high-frequency voltage signal injection and the offset voltage for accurate detection is used. As a result, the permanent magnet poles are is determined by acquiring the maximum value of the induced current using the virtual dq-axis.

A Study on the Fabrication of Polarimetric Fiber Optic Current Sensor (편광측정법에 의한 광섬유 전류 센서 제작에 관한 연구)

  • Jang, Nam-Young;Chio, Pyung-Suk;Eun, Jae-Jeong;Park, Hae-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.41 no.6
    • /
    • pp.33-41
    • /
    • 2004
  • In this paper, a polarimetric fiber optic current sensor(P-FOCS) is experimented and fabricated, and then a possibility to the commercial utilization of the P-FOCS is also investigated. The P-FOCS measures an applied current by a Faraday rotation linearly proportional to a magnetic field generated by the applied current. The bending-induced linear birefringence in the sensing fiber is minimized by using the low birefringent fiber. Also, all fiber-optic components are used to avoid optical losses coming from the use of bulk components. A signal processing circuit is constructed and used to eliminate the effects of intensity variations in the output signal due to losses coming from misalignments of components such as fiber connectors. Using the optical source of 632.8nm wavelength, Faraday rotation is measured by passing through the sensing fiber within the solenoid of about 1500 turns which is equivalent to a current source of about 7500A. In the range of 1000A to 7500A, the measurement error for linearity is within about 1.5%.

Design of Low Power Current Memory Circuit based on Voltage Scaling (Voltage Scaling 기반의 저전력 전류메모리 회로 설계)

  • Yeo, Sung-Dae;Kim, Jong-Un;Cho, Tae-Il;Cho, Seung-Il;Kim, Seong-Kweon
    • The Journal of the Korea institute of electronic communication sciences
    • /
    • v.11 no.2
    • /
    • pp.159-164
    • /
    • 2016
  • A wireless communication system is required to be implemented with the low power circuits because it uses a battery having a limited energy. Therefore, the current mode circuit has been studied because it consumes constant power regardless of the frequency change. However, the clock-feedthrough problem is happened by leak of stored energy in memory operation. In this paper, we suggest the current memory circuit to minimize the clock-feedthrough problem and introduce a technique for ultra low power operation by inducing dynamic voltage scaling. The current memory circuit was designed with BSIM3 model of $0.35{\mu}m$ process and was operated in the near-threshold region. From the simulation result, the clock-feedthrough could be minimized when designing the memory MOS Width of $2{\mu}m$, the switch MOS Width of $0.3{\mu}m$ and dummy MOS Width of $13{\mu}m$ in 1MHz switching operation. The power consumption was calculated with $3.7{\mu}W$ at the supply voltage of 1.2 V, near-threshold voltage.

Design of a High Performance Multiplier Using Current-Mode CMOS Quaternary Logic Circuits (전류모드 CMOS 4치 논리회로를 이용한 고성능 곱셈기 설계)

  • Kim, Jong-Soo;Kim, Jeong-Beom
    • Journal of IKEEE
    • /
    • v.9 no.1 s.16
    • /
    • pp.1-6
    • /
    • 2005
  • This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

  • PDF

The Design of High-Speed, High-Resolution D/A Converter for Digital Image Signal Processing with Deglitching Current Cell (글리치 방지 전류원을 이용한 고속 고정밀 디지탈 영상 신호 처리용 D/A 변환기 설계)

  • Lee, Seong-Dae;Jeong, Gang-Min
    • The Transactions of the Korea Information Processing Society
    • /
    • v.1 no.4
    • /
    • pp.469-478
    • /
    • 1994
  • In this paper, a high speed, high resolution information processing digital- analog converter was designed for high definition color graphic, digital image signal processing, HDTV. For high speed operation, matrix type current cell array, latch which is not use pipelined, and two dimensional structure decoder using transmission gate were designed. It is adopted to fast-conversion, low-power implementation and exhibited high performance at linearity and accuracy. To reduce silicon area and to maintain resolution, current cell array composed of weighted and non-weighted current cells. In this paper, deglitching current cell design for high accuracy, new switching algorithm assert to reduce switching error. It's This circuit dissipates 130W with a 5-V power supply, and operate above 100MHz with 10 bit resolution.

  • PDF