• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.423-424
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• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1235-1242
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• 2008

In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.

• Journal of IKEEE
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• v.22 no.4
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• pp.1025-1030
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• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

• Journal of IKEEE
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• v.12 no.3
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• pp.176-183
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• 2008

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit as a block. The Saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 95% at 100mA output current. And DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.12
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• pp.7287-7291
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• 2014

A CDTA (current differencing transconductance amplifier) is an active building block for current mode analog signal processing with the advantages of high linearity and a wide frequency bandwidth. In addition, it can generate a stable voltage because all the differencing input current flows to the grounded devices. In this paper, a new small signal equivalent circuit is proposed to analyze a CDTA. The proposed small signal equivalent circuit provides greater precision in analyzing the magnitude and frequency response than its previous counterparts because it considers the parasitic components of the input, internal and output terminal. In addition, observations of the changes made in various devices, such as the resistor (Rz) confirmed that those devices heavily influence the characteristics of CDTA. The designed parameters of the proposed small signal equivalent circuit of the CDTA provides convenience and accuracy in the further design of analog integrated circuits. For verification purposes, a 2.5 MHz low pass filter was designed on the HSPICE simulation program using the proposed small signal equivalent circuit of CDTA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1663-1670
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• 2006

Single crystal Fe thin films were grown directly onto n-Si(111) substrates by pulsed electrodeposition. Cyclic Voltammogram(CV) indicated that the $Fe^{2+}/n-Si(111)$ interface shows a good diode behavior by forming a Schottky barrier. From Mott-Schottky (MS) relation, it is found that the flat-band potential of n-Si(111) substrate and equilibrium redox potential of $Fet^{2+}$ ions are -0.526V and -0.316V, respectively. The nucleation and growth kinetics at the initial reaction stages of Fe/n-Si(111) substraste was studied by current transients. Current transients measurements have indicated that the deposition process starts via instantaneous nucleation and 3D diffusion limited growth. After the more deposition, the deposition flux of Fe ions was saturated with increase of deposition time. from the as-deposited sample obtained using the potential pulse of 1.4V and 300Hz, it is found that Fe nuclei grows to three dimensional(3D) islands with the average size of about 100nm in early deposition stages. As the deposition time increases, the sizes of Fe nuclei increases progressively and by a coalescence of the nuclei, a continuous Fe films grow on the Si surface. In this case, the Fe films show a highly oriented columnar structure and x-ray diffraction patterns reveal that the phase ${\alpha}-Fe$ grows on the n-Si(111) substrates.

• Journal of the Korea Convergence Society
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• v.8 no.5
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• pp.161-167
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• 2017

We have fabricated and characterized $32{\times}32$ photonic quantum ring (PQR) laser arrays uniformly operable with $0.98{\mu}A$ per ring at room temperature. The typical threshold current, threshold current density, and threshold voltage are 20 mA, $0.068A/cm^2$, and 1.38 V. The top surface emitting PQR array contains GaAs multiquantum well active regions and exhibits uniform characteristics for a chip of $1.65{\times}1.65mm^2$. The peak power wavelength is $858.8{\pm}0.35nm$, the relative intensity is $0.3{\pm}0.2$, and the linewidth is $0.2{\pm}0.07nm$. We also report the wavelength division multiplexing system experiment using angle-dependent blue shift characteristics of this laser array. This photonic quantum ring laser has angle-dependent multiple-wavelength radial emission characteristics over about 10 nm tuning range generated from array devices. The array exhibits a free space detection as far as 6 m with a function of the distance.

• Journal of the Korean Electrochemical Society
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• v.10 no.3
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• pp.196-202
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• 2007

The performance characteristics of the polymer electrolyte fuel cells (PEFCS) were investigated under various humidification conditions at steady-state and transient conditions. The PEFC studied in this study was characterized by I-V curves in the potentiostatic mode and EIS (electrochemical impedance spectroscopy). The I-V curves representing steady-state performance were obtained from OCV to 0.25 V, and the dynamic performance responses were obtained at some voltages. The effects of anodic external humidification were measured by varying relative humidity of hydrogen from 20% to 100% while dry air was supplied in the cathode. At the high voltage region, the performance became higher with the increase of the temperature, while at the low voltage region, the performance decreased with the increase of temperature. The EIS showed that ohmic losses were larger at the dry condition of membrane and the effects of mass transport losses increased remarkably when the external and self-humidification were high. The dynamic responses were also monitored by changing the voltage of the PEFC instantly. As the temperature increased, the current reached steady-state earlier. The self-humidification with the generated water delayed the stabilization of the current except for low voltage conditions.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.