• Title/Summary/Keyword: 전류유지모드

Search Result 54, Processing Time 0.02 seconds

The optical CT output signal characteristic according to temperature change (온도변화에 따른 광CT의 출력 특성)

  • Son, Hyun-Mok;Ahn, Mi-Kyoung;Heo, Soon-Young;Jeon, Jea-Il;Park, Won-Zoo;Lee, Kwang-Sik;Kim, Jung-Bae;Kim, Min-Soo
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
    • /
    • 2004.05a
    • /
    • pp.29-33
    • /
    • 2004
  • In this paper, we took the basic experiment in order to explore the characteristics of optical CT(optical current transformer) for measuring high current in a superhigh voltage condition using faraday effect and wrote that. We used the 1,310[nm] Laser Diode for the source of light and PIN-Photodiode for receiver. The transmission line of light was composed of the single-mode fiber of 30[m] which could maintain the state of polarization in the optical fiber. The range of current was from 400[A] to 1300[A]. In addition, the temperature ranged from $20[^{\circ}C}]\;to\;50[^{\circ}C]$. In a same experiment condition, a power magnitude increases in proportion as input current is increasing and temperature become low. The maximum ratio of error in temperature of $50[^{\circ}C]$ appears 0.15[%] and the 0.16[%], 1.24[%] and 0.07[%] is ratio of error in respectively $40[^{\circ}C],\;30[^{\circ}C],\;and\;20[^{\circ}C]$.

  • PDF

Analyses of Larg Cell Area MCFC System Dynamics (대면적 용융탄산염 연료전지 시스템 동특성 분석)

  • 강병삼;고준호;이충곤;임희천
    • Journal of Energy Engineering
    • /
    • v.8 no.4
    • /
    • pp.592-604
    • /
    • 1999
  • The steady state and dynamic characteristics of large cell area MCFC stacks were analyzed to solve the problems such as temperature difference generated in stacks and pressure difference between anode and cathode. Manipulated variables (current density, duel utilization rate, oxidant utilization rate) and controlled variables (temperature difference, anode and cathode pressure difference) which had an important effect on the MCFC stack performance were determined using operation results of two types of MCFC stacks (5kW (3,000 $\textrm{cm}^2$, 20 ea). 3kW (6,000 $\textrm{cm}^2$, 5ea)). The stability and transfer function representing system dynamics were obtained by steady state gain rate which showed the relative change between MVs and CVs. The transfer function was a 3$\times$3 matrix and a typical first order system without time delay. The optimal operating condition of large cell area MCFC stacks could be determined by analyzing dynamic characteristics. In case of a 5 kW MCFC stack, pressurized operation with recycle flow should be used to control the outlet temperature less than 68$0^{\circ}C$ and to control the MCFC system effectively. MIMO control or decoupler should be used to remove the interaction between MVs and CVs. This result will be used as important data in determining the control structure design and operation mode of large cell area MCFC systems in the future.

  • PDF

The Study on New Radiating Structure with Multi-Layered Two-Dimensional Metallic Disk Array for Shaping flat-Topped Element Pattern (구형 빔 패턴 형성을 위한 다층 이차원 원형 도체 배열을 갖는 새로운 방사 구조에 대한 연구)

  • 엄순영;스코벨레프;전순익;최재익;박한규
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.13 no.7
    • /
    • pp.667-678
    • /
    • 2002
  • In this paper, a new radiating structure with a multi-layered two-dimensional metallic disk array was proposed for shaping the flat-topped element pattern. It is an infinite periodic planar array structure with metallic disks finitely stacked above the radiating circular waveguide apertures. The theoretical analysis was in detail performed using rigid full-wave analysis, and was based on modal representations for the fields in the partial regions of the array structure and for the currents on the metallic disks. The final system of linear algebraic equations was derived using the orthogonal property of vector wave functions, mode-matching method, boundary conditions and Galerkin's method, and also their unknown modal coefficients needed for calculation of the array characteristics were determined by Gauss elimination method. The application of the algorithm was demonstrated in an array design for shaping the flat-topped element patterns of $\pm$20$^{\circ}$ beam width in Ka-band. The optimal design parameters normalized by a wavelength for general applications are presented, which are obtained through optimization process on the basis of simulation and design experience. A Ka-band experimental breadboard with symmetric nineteen elements was fabricated to compare simulation results with experimental results. The metallic disks array structure stacked above the radiating circular waveguide apertures was realized using ion-beam deposition method on thin polymer films. It was shown that the calculated and measured element patterns of the breadboard were in very close agreement within the beam scanning range. The result analysis for side lobe and grating lobe was done, and also a blindness phenomenon was discussed, which may cause by multi-layered metallic disk structure at the broadside. Input VSWR of the breadboard was less than 1.14, and its gains measured at 29.0 GHz. 29.5 GHz and 30 GHz were 10.2 dB, 10.0 dB and 10.7 dB, respectively. The experimental and simulation results showed that the proposed multi-layered metallic disk array structure could shape the efficient flat-topped element pattern.

Three Phase Dynamic Current Mode Logic against Power Analysis Attack (전력 분석 공격에 안전한 3상 동적 전류 모드 로직)

  • Kim, Hyun-Min;Kim, Hee-Seok;Hong, Seok-Hee
    • Journal of the Korea Institute of Information Security & Cryptology
    • /
    • v.21 no.5
    • /
    • pp.59-69
    • /
    • 2011
  • Since power analysis attack which uses a characteristic that power consumed by crypto device depends on processed data has been proposed, many logics that can block these correlation originally have been developed. DRP logic has been adopted by most of logics maintains power consumption balanced and reduces correlation between processed data and power consumption. However, semi-custom design is necessary because recently design circuits become more complex than before. This design method causes unbalanced design pattern that makes DRP logic consumes unbalanced power consumption which is vulnerable to power analysis attack. In this paper, we have developed new logic style which adds another discharge phase to discharge two output nodes at the same time based on DyCML to remove this unbalanced power consumption. Also, we simulated 1bit fulladder to compare proposed logic with other logics to prove improved performance. As a result, proposed logic is improved NED and NSD to 60% and power consumption reduces about 55% than any other logics.