• Title/Summary/Keyword: 전계효과 트랜지스터

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Random Dopant Fluctuation Effects of Tunneling Field-Effect Transistors (TFETs) (터널링 전계효과 트랜지스터의 불순물 분포 변동 효과)

  • Jang, Jung-Shik;Lee, Hyun Kook;Choi, Woo Young
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.12
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    • pp.179-183
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    • 2012
  • The random dopant fluctuation (RDF) effects of tunneling field-effect transistors (TFETs) have been observed by using atomistic 3-D device simulation. Due to extremely low body doping concentration, the RDF effects of TFETs have not been seriously investigated. However, in this paper, it has been found that the randomly generated and distributed source dopants increase the variation of threshold voltage ($V_{th}$), drain induced current enhancement (DICE) and subthreshold slope (SS) of TFETs. Also, some ways of relieving the RDF effects of TFETs have been presented.

Test-bed of Total Ionizing Dose (TID) Test by Cosmic Rays for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (금속-산화막 반도체 전계효과 트랜지스터의 우주방사선에 의한 총이온화선량 시험을 위한 테스트 베드)

  • Sin, Gu-Hwan;Yu, Gwang-Seon;Gang, Gyeong-In;Kim, Hyeong-Myeong;Jeong, Seong-In
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.34 no.11
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    • pp.84-91
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    • 2006
  • Recently, all the electrical parts for satellite application are required more strong against cosmic rays, because spacecraft's life time and function are depending on the their conditions. Also, a TID effect test was undertaken with units and/or subsystems which are already assembled on the PCB in past time. However, it is very hard to know and analyze that some abnormal states are appeared after launch. Moreover, it is necessary to perform a test of TID effects based on the parts level for preparing preliminary data in cosmic rays. Therefore, this paper presents a test-bed to perform a TID effect test of Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) which is a fundamental element for electronics.

그래핀 전계효과 트랜지스터의 광응답 특성

  • Lee, Dae-Yeong;Min, Mi-Suk;Ra, Chang-Ho;Lee, Hyo-Yeong;Yu, Won-Jong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.193-194
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    • 2012
  • 그래핀(graphene)은 탄소원자가 육각형 벌집 모양 배열의 격자구조를 가지는 원자 한층 두께의 이차원 물질이다. 그래핀은 전도띠(conduction band)와 가전자띠(valence band)가 한 점에서 만나고 에너지와 역격자의 k 벡터가 선형적으로 비례하는 에너지 구조를 가진다. 이로 인해 그래핀은 매우 빠른 전하 이동도를 가지며 원자 한 층의 두께임에도 불구하고 약 2.3%의 빛을 흡수할 수 있으며 자외선 영역부터 적외선 영역까지의 넓은 파장대의 빛을 흡수 할 수 있다. 이와 같은 그래핀의 우월한 성질을 이용하면 광 응답에 고속으로 반응하고 높은 주파수의 광통신에서도 작동 할 수 있는 그래핀 광소자를 제작할 수 있게 된다. 하지만 미래의 고속 그래핀 광소자를 실현하기에 앞서 그래핀의 광응답에 대한 정확한 이해가 필요하다. 그리하여 본 연구에서는 그래핀 광소자를 제작하고 광소자의 광응답 전기적 성질을 분석하여 그래핀의 광응답 특성을 얻어내고자 실험을 진행하였다. 그래핀을 채널 물질로 하고 소스, 드레인, 후면 게이트를 가지는 일반적인 그래핀 전계효과 트랜지스터(field-effect transistor)를 제작하고 채널에 빛을 비추고 비추지 않은 상태에서의 전기적 성질을 측정하고 그 때 얻어진 그래프의 광응답의 원인을 조사하였다. 이 때 얻어지는 $I_D-V_G$ 그래프가 광 조사 시 왼쪽으로 이동하게 되는데 이의 원인을 각 게이트 전압 구간별로 $I_D$-t 그래프를 획득하여 분석하였다. 또한 광원에 펄스를 인가하여 펄스 형태의 광원을 그래핀 전계효과 트랜지스터에 조사시키고 이에 따른 전기적 성질 변화를 관찰하였다 이 때 다양한 게이트 전압이 인가된 상태에서 레이저 펄스 광원에 의한 광전류를 검출하였으며 이를 분석하였다.

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Study of monolithic 3D integrated-circuit consisting of tunneling field-effect transistors (터널링 전계효과 트랜지스터로 구성된 3차원 적층형 집적회로에 대한 연구)

  • Yu, Yun Seop
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.5
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    • pp.682-687
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    • 2022
  • In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

Field-effect Transistors Based on a Van der Waals Vertical Heterostructure Using CVD-grown Graphene and MoSe2 (화학기상증착법을 통해 합성된 그래핀 및 MoSe2를 이용한 반데르발스 수직이종접합 전계효과 트랜지스터)

  • Seon Yeon Choi;Eun Bee Ko;Seong Kyun Kwon;Min Hee Kim;Seol Ah Kim;Ga Eun Lee;Min Cheol Choi;Hyun Ho Kim
    • Journal of Adhesion and Interface
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    • v.24 no.3
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    • pp.100-104
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    • 2023
  • Van der Waals heterostructures have garnered significant attention in recent research due to their excellent electronic characteristics arising from the absence of dangling bonds and the exclusive reliance on Van der Waals forces for interlayer coupling. However, most studies have been confined to fundamental research employing the Scotch tape (mechanical exfoliation) method. We fabricated Van der Waals vertical heterojunction transistors to advance this field using materials exclusively grown via chemical vapor deposition (CVD). CVDgrown graphene was patterned through photolithography to serve as electrodes, while CVD-grown MoSe2 was employed as the pickup/transfer material, resulting in the realization of Van der Waals heterojunction transistors with interlayer charge transfer effects. The electrical characteristics of the fabricated devices were thoroughly examined. Additionally, we observed variations in the transistor's performance based on the presence of defects in MoSe2 layer.

Investigation of the electrical characteristics of monolithic 3-dimensional static random access memory consisting of feedback field-effect transistor (피드백 전계 효과 트랜지스터로 구성된 모놀리식 3차원 정적 랜덤 액세스 메모리 특성 조사)

  • Oh, Jong Hyeok;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2022.10a
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    • pp.115-117
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    • 2022
  • The electrical characteristics of the monolithic 3-dimensional static random access memory consisting of a feedback field-effect transistor (M3D-SRAM-FBFET) was investigated using technology computer-aided design (TCAD). The N-type FBFET and N-type MOSFET are designed with fully depleted silicon on insulator (FDSOI), and those are located at bottom and top tiers, respectively. For the M3D-SRAM-FBFET, as the supply voltage decreased from 1.9 V to 1.6 V, the reading on-current decreased approximately 10 times.

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