• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.414-418
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• 2016

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.419-427
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• 2016

In this paper, a 64b small-area MTP memory IP is designed. A VPPL (=VPP/3) regulator and a VNN (=VNN/3) charge pump are removed since the inhibit voltages of an MTP memory cell are all 0V instead of the conventional voltages of VPP/3 and VNN/3. Also, a VPP charge pump is removed since the VPP program voltage is supplied from an external pad. Furthermore, a VNN charge pump is designed to provide its voltage of -VPP as a one-stage negative charge pump using the VPP voltage. The layout size of the designed 64b MTP memory IP with MagnaChip's $0.18{\mu}m$ BCD process is $377.585{\mu}m{\times}328.265{\mu}m$ (=0.124mm2). Its DC-DC converter related layout size is 76.4 percent smaller than its conventional counterpart.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7A
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• pp.547-556
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• 2003

This paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for low-area elliptic curve cryptographic processor. The proposed arithmetic unit, which is linear feed back shift register (LFSR) architecture, is designed by using hardware sharing between the binary GCD algorithm and the most significant bit (MSB)-first multiplication scheme, and it can perform both division and multiplication in GF(2$^{m}$ ). In other word, the proposed architecture produce division results at a rate of one per 2m-1 clock cycles in division mode and multiplication results at a rate of one per m clock cycles in multiplication mode. Analysis shows that the computational delay time of the proposed architecture, for division, is less than previously proposed dividers with reduced transistor counts. In addition, since the proposed arithmetic unit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed novel architecture can be used for both division and multiplication circuit of elliptic curve cryptographic processor. Specially, it is well suited to low-area applications such as smart cards and hand held devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.40-47
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• 2009

In this paper, we present the design of a source driver of QVGA scale TFT-LCD driver IC which uses a mixed driving method and performs $\gamma$-correction to improve image. The source driver with 240 RGB ${\times}$ 320 dots resolution drives a TFT-LCD panel through 720 channels and implements 262k colors using 18-bit RGB data format. The mixed driving method is a mixture the channel amp. driving method with high drivability and the gray amp. driving method with small area, which remarkably reduces channel driver areas. The driver has been designed using the $0.35{\mu}m$ Magnachip embedded DRAM technology and simulated using the HSPICE simulator. The results show that our source driver operates well with y-correction and the channel driver has $17{\mu}s$ channel driving time with only 78 driving amplifiers and control logic.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.52-57
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• 2009

This paper presents a low-noise low-dropout linear regulator that is suitable for on-chip integration with RF transceiver ICs. In the bandgap reference, a stacked diode structure is adopted for saving silicon area as well as maintaining low output noise characteristic. Theoretical analysis for supporting the approach is also described. The linear regulator is fabricated in $0.18{\mu}m$ CMOS process. It operates with an input voltage range of 2.2 V - 5 V and provide the output voltage of 1.8 V and the output current up to 90 mA. The measured line and load regulation is 0.04%/V and 0.46%, respectively. The output noise voltage is measured to be 479 nV/$^\surd{Hz}$ and 186 nV/$^\surd{Hz}$ from 100 Hz and 1 kHz offset, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Review of KIISC
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• v.29 no.5
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• pp.31-36
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• 2019

초고속, 초저지연, 초연결 특성으로 대표되는 5G 시대가 도래함에 따라 새로운 통신 환경과 서비스 환경에 적합한 암호기술이 요구되고 있다. IoT 환경 등 자원이 제약된 기기를 위한 저면적/저전력 암호기술, 자율 주행 등 실시간 처리를 위한 저지연 암호기술 등 경량암호에 대한 요구사항 또한 다변화되고 있다. 본 고에서는 SPECK/SIMON, LEA 등으로 대표되는 경량 블록암호와 초저지연 암호기술에 대해 살펴보고 NIST에서 진행 중인 경량암호 공모사업을 소개한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.31-39
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• 2011

In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.467-468
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• 2019

본 논문은 차량용 장거리 레이더를 위한 저 위상잡음 77GHz CMOS 전압제어발진기를 제안한다. 이러한 회로는 낮은 위상잡음을 가지도록 설계되어 있고, 1.5볼트 전원에서 동작한다. 제안한 회로는 TSMC $0.13{\mu}m$ 고주파 CMOS 공정으로 설계하였다. 제안한 회로는 최근 발표된 연구결과에 비해 저 위상잡음, 저 전력 및 적은 면적 특성을 보였다.

• Proceedings of the Korea Water Resources Association Conference
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• 2021.06a
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• pp.391-391
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• 2021

최근에는 도시에는 불투수 면적의 증가로 지면 침투량이 줄어들고 유출량이 증가되고 있다. 또한 지면에서의 먼지 등 비점오염원의 유출로 인한 수질악화도 진행되는 경우가 많다. 그러므로 도시의 개발에 따른 악영향을 최소화하기 위해 다양한 저영향개발기법(Low Impact Development)을 도입하여 도시 물순환 건전성을 확보하기 위해 노력하고 있다. 본 연구에서는 도시 유역에서의 유출량 분석을 위해 저영향개발기법 중 투수성포장과 옥상녹화 등을 적용하여 침투량의 증가와 유출량 감소 결과를 분석하였다. 투수성포장과 옥상녹화의 영향이 크지는 않지만, 도시에서의 유출량 저감에 영향을 미칠 수 있는 것으로 분석되었으며, 향후 지속적인 도시 물순환 건 전성 확보연구의 기초 자료로 활용될 수 있을 것으로 보인다. 그 결과는 도시 개발 계획의 우선순위를 결정하는데 사용될 수 있어서, 도시 공간의 삶의 질이 향상될 것이다.