• 제목/요약/키워드: 저전력알고리즘

검색결과 454건 처리시간 0.026초

A High-Level Data Path Allocation Algorithm for Low Power Architecture (저 전력 아키텍처를 위한 상위 레벨 데이터 패스 할당 알고리즘)

  • Lin, Chi-Ho
    • Journal of IKEEE
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    • 제7권2호
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    • pp.166-171
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    • 2003
  • In this paper, we propose a minimal power data path allocation algorithm for low power circuit design. The proposed algorithm minimizes switching activity for input variables in scheduled CDFG. Allocations are further divided into the tasks of register allocation and module allocation. The register allocation algorithm execute that it eliminate spurious switching activity in functional unit and minimize the numbers of multiplexer. Also, resource allocation method selects a sequence of operations for a module such that the switching activity is reduced. Therefore, the algorithm executes to minimize the switching activity of input values, sequence of operations and number of multiplexer. Experimental results using benchmarks show that power is reduction effect from 13% to 17% power consumption, when compared with the Genesis-lp high-level synthesis system.

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Obstacle Avoidance Algorithm of Hybrid Wheeled and Legged Mobile Robot Based on Low-Power Walking (복합 바퀴-다리 이동형 로봇의 저전력 보행 기반 장애물 회피 알고리즘)

  • Jeong, Dong-Hyuk;Lee, Bo-Hoon;Kim, Yong-Tae
    • Journal of the Korean Institute of Intelligent Systems
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    • 제22권4호
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    • pp.448-453
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    • 2012
  • There are many researches to develop robots that improve its mobility to adapt in various uneven environments. In the paper, a hybrid wheeled and legged mobile robot is designed and a obstacle avoidance algorithm is proposed based on low power walking using LRF(Laser Range Finder). In order to stabilize the robot's motion and reduce energy consumption, we implement a low-power walking algorithm through comparison of the current value of each motors and correction of posture balance. A low-power obstacle avoidance algorithm is proposed by using LRF sensor. We improve walking stability by distributing power consumption and reduce energy consumption by selecting a shortest navigation path of the robot. The proposed methods are verified through walking and navigation experiments with the developed hybrid robot.

Hardware Implementation of Low-power Display Method for OLED Panel using Adaptive Luminance Decreasing (적응적 휘도 감소를 이용한 OLED 패널의 저전력 디스플레이 방법 및 하드웨어 구현)

  • Cho, Ho-Sang;Choi, Dae-Sung;Seo, In-Seok;Kang, Bong-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • 제17권7호
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    • pp.1702-1708
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    • 2013
  • OLED has good efficiency of power consumption by having no power consumption from black color as different with LCD. when it has white color, all RGB pixel should be glowing with high power consumption and that can make it has short life time. This paper suggest the way of low power consumption for OLED panel using adaptive luminance enhancement with color compensation and implement it as hardware. This way which is based on luminance information of input image makes converted luminance value from each pixel in real time. There is with using the basic idea of chromaticity reduction algorithm, showing new algorithm of color correction. And performance of proposed method was confirmed by comparing the conventional method in experiments about 48.43% current reduction. The proposed method was designed by Verilog HDL and was verified by using OpenCV and Windows Program.

Three Phase Voltage Sag Generator for LVRT Algorithm Verification with LVRT Requirements of Various Grid Codes (다양한 국가의 계통 코드를 만족하는 LVRT 알고리즘 검증용 3상 저전압 발생장치)

  • Lee, Jongpil;Lee, Kyoung-Jun;Shin, Dongsul;Kim, Taejin;Yoo, Dongwook;Cho, DongHwan
    • Proceedings of the KIPE Conference
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    • 전력전자학회 2013년도 전력전자학술대회 논문집
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    • pp.149-150
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    • 2013
  • 본 논문에서는 계통 이상 시 요구되는 대용량 분산발전용 계통연계형 PCS의 LVRT(Low Voltage Ride Through) 알고리즘을 시험하기 위한 저전압발생장치를 제안한다. 제안한 저전압 발생장치는 변압기 tap 변경 방식을 적용하여 원하는 시점과 전압레벨에 저전압 조건을 만들 수 있는 시스템을 구성하고 대용량 확장성을 고려하여 모든 나라의 LVRT 계통 코드를 만족 할 수 있다. 제안한 저전압 발생 시스템의 나라별 LVRT 코드 발생 특성을 살펴보고 10kVA급 저전압발생 시스템을 통해 유용성을 확인한다.

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Low Power Scan Testing and Test Data Compression for System-On-a-Chip (System-On-a-Chip(SOC)에 대한 효율적인 테스트 데이터 압축 및 저전력 스캔 테스트)

  • 정준모;정정화
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • 제39권12호
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    • pp.1045-1054
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    • 2002
  • We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

Low-Energy Intra-Task Voltage Scheduling using Static Timing Analysis (정적 시간 분석을 이용한 저전력 태스크내 전압 스케줄링)

  • Sin, Dong-Gun;Kim, Ji-Hong;Lee, Seong-Su
    • Journal of KIISE:Computer Systems and Theory
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    • 제28권11호
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    • pp.561-572
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    • 2001
  • Since energy consumption of CMOS circuits has a quadratic dependency on the supply voltage, lowering the supply voltage is the most effective way of reducing energy consumption. We propose an intra-task voltage scheduling algorithm for low-energy hard real-time applications. Based on a static timing analysis technique, the proposed algorithm controls the supply voltage within an individual task boundary. By fully exploiting all the slack times, as scheduled program by the proposed algorithm always complete its execution near the deadline, thus achieving a high energy reduction ratio. In order to validate the effectiveness of the proposed algorithm, we built a software tool that automatically converts a DVS-unaware program into an equivalent low-energy program. Experimental results show that the low-energy version of an MPEG-4 encoder/decoder (converted by the software tool) consumes less than 7~25% of the original program running on a fixed-voltage system with a power-down mode.

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An Efficient Data Transmission Strategy using Adaptive-Tier Low Transmission Power Schedule in a Steady-state of BMA (적응형 저전력 전송 기법을 사용한 효율적인 BMA 데이터 전송 기술)

  • Kim, Sang-Chul
    • Journal of the Korea Society of Computer and Information
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    • 제15권5호
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    • pp.103-111
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    • 2010
  • This paper proposes an efficient data transmission strategy using adaptive-tier low transmission power schedule in a TDMA-based ad hoc MAC protocol. Since the network resource of ad hoc networks has the characteristic of reassignment due to the multiple interferences and the contention-based limited wireless channel, the efficient time slot assignment and low power transmission scheme are the main research topics in developing ad hoc algorithms. Based on the proposed scheme of interference avoidance when neighbor clusters transmit packets, this paper can minimize the total energy dissipation and maximize the utilization of time slot in each ad hoc node. Simulation demonstrates that the proposed algorithm yields 15.8 % lower energy dissipation and 4.66% higher time slot utilization compared to the ones of two-tier conventional energy dissipation model.

A Power Saving Routing Scheme in Wireless Networks (무선망에서 소비 전력을 절약하는 라우팅 기법)

  • 최종무;김재훈;고영배
    • Journal of KIISE:Information Networking
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    • 제30권2호
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    • pp.179-188
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    • 2003
  • Advances in wireless networking technology has engendered a new paradigm of computing, called mobile computing, in which users carrying portable devices have access to a shared infrastructure independent of their physical locations. Wireless communication has some restraints such as disconnection, low bandwidth, a variation of available bandwidth, network heterogeneity, security risk, small storage, and low power. Power adaptation routing scheme overcome the shortage of power by adjusting the output power, was proposed. Existing power saving routing algorithm has some minor effect such as seceding from shortest path to minimize the power consumption, and number of nodes that Participate in routing than optimal because it select a next node with considering only consuming power. This paper supplements the weak point in the existing power saving routing algorithm as considering the gradual approach to final destination and the number of optimal nodes that participate in routing.

An Efficient Data Path Synthesis Algorithm for Low-Power (저전력 데이타-경로를 위한 효율적인 고수준 합성 알고리즘)

  • Park, Chae-Ryung;Kim, Young-Tae;Kim, Tae-Hwan
    • Journal of KIISE:Computer Systems and Theory
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    • 제27권2호
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    • pp.227-233
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    • 2000
  • In this paper, we present a new high-level data path synthesis algorithm which solves the two design problems, namely, scheduling and allocation, with power minimization as a key design parameter. From the observations in previous works on data path synthesis for low power, we derive an integer programming (IP) formulation for the problem, from which we then develop an efficient heuristic to carry out the scheduling and allocation simultaneously. Our experimental results demonstrate that the proposed algorithm is very effective in saving power consumption of circuits significantly.

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Fast Adaptation Techniques of Compensation Coefficient of Active Noise Canceller using Binary Search Algorithm (이진 탐색 알고리즘을 이용한 능동 노이즈 제거용 보정 계수 고속 적용 기법)

  • An, Joonghyun;Park, Daejin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • 제25권11호
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    • pp.1635-1641
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    • 2021
  • Portable systems with built-in active noise control is required low power operation. Excessive anti noise search operation can lead to rapid battery consumption. A method that can adaptively cancel noise according to the operating conditions of the system is required and the methods of reducing power are becoming very important key feature in today's portable systems. In this paper, we propose the method of active noise control(ANC) using binary search algorithm in noisy systems. The implemented architecture detects a frequency component considered as noise from the input signal and by using the binary search algorithm, the system find out an appropriate amplitude value for anti-noise in a much faster time than the general linear search algorithm. Through the experimental results, it was confirmed that the proposed algorithm performs a successful functional operation.