• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.1-12
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• 2010

Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.39 no.1
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• pp.219-225
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• 2019

Computing low temperature performance of asphalt mixture is one of the important tasks especially for cold regions. It is well known that experimental creep testing work is needed for computation of thermal stress and critical cracking temperature of given asphalt mixture. Thermal stress is conventionally computed through two steps of computation. First, the relaxation modulus is generated thorough the inter-conversion of the experimental creep stiffness data through the application of Hopkins and Hamming's algorithm. Secondly, thermal stress is numerically estimated solving the convolution integral. In this paper, one-step thermal stress computation methodology based on the Laplace transformation is introduced. After the extensive experimental works and comparisons of two different computation approaches, it is found that Laplace transformation application provides reliable computation results compared to the conventional approach: using two step computation with Hopkins and Hamming's algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.532-542
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• 2009

Dynamic Thermal Management (DTM) technique is generally used for reducing the peak temperature (hotspot) in the microprocessors. Despite the advantages of lower cooling cost and improved stability, the DTM technique inevitably suffers from performance loss. This paper proposes the DualFloating-Point Adders Architecture to minimize the performance loss due to thermal problem when the floating-point applications are executed. During running floating-point applications, only one of two floating-point adders is used selectively in the proposed architecture, leading to reduced peak temperature in the processor. We also propose a new floorplan technique, which creates Space for Heat Transfer Delay in the processor for solving the thermal problem due to heat transfer between adjacent hot units. As a result, the peak temperature drops by $5.3^{\circ}C$ on the average (maximum $10.8^{\circ}C$ for the processor where the DTM is adopted, consequently giving a solution to the thermal problem. Moreover, the processor performance is improved by 41% on the average by reducing the stall time due to the DTM.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10b
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• pp.451-456
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• 2007

칩의 온도 상승에 대한 우려는 최근 점점 가시화되고 있다. 즉, 설계 집적도의 증가에 따른 전력 소모 밀도의 증가는 바로 칩 온도 상승으로 이어지고 있다. 이러한 칩 온도 상승은 성능 저하와 패키징 비용 증가 뿐 만 아니라, 칩의 신뢰성 칩 수명에서도 나쁜 악영향을 초래한다. 본 연구는 칩 온도 상승을 억제하기 위한 상위 단계 합성을 제안하고 있다. 구체적으로 본 연구의 핵심은 다중 전압 할당과 연산에 대한 모듈 바인딩(배정)을 동시에 고려한 새로운 저온도 설계 기법을 시도한다. 과거의 이중 threshold 전압 할당과 모듈 바인딩은 각각 누설 전류와 동적 전류를 줄이기 위해 적용된 반면 본 연구는 온도 최소화 측면에서 연구를 시도한 점에서 다른 설계 가능성을 보여 준다고 하겠다.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• The Journal of the Acoustical Society of Korea
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• v.15 no.5
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• pp.53-60
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• 1996

In this study, a design methodology for thermoacoustic refrigerator systems is proposed based on the thermal conduction and acoustic theories, and physical characteristics of an actual thermoacoustic refrigerator are investigated. Especially, the resonator is designed for minimizing the energy loss at cold end, and the position and length of the capillary stack are optimized in order to get a large temperature difference between hot and cold ends. Experimental results show that a maximun temperature difference of 22.7$^{\circ}$ and a temperature of 4.3$^{\circ}$C at cold end are obtained by supplying an electrical input of 33W without any thermal load at cold end.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.46-46
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• 2009

과거 고강도강 용접부에서 발생하는 저온균열은 주로 용접열영향부에서 발생하였는데, 이러한 문제점을 해결하기 위하여 강재 메이커들은 고강도강의 용접성을 향상시키고자 노력하였다. 이러한 노력의 결과로 TMCP, HSLA 강 등이 개발되었고 이들 강재는 예열온도를 저하시킬 수 있다는 장점 때문에 보편화되어 사용되었다. 이러한 강재는 모재 예열온도를 기준으로 적용하게 되면 용착금속에서 저온균열이 발생하는 경우가 있다. 따라서 이제는 용접재료의 용접성, 즉 용접재료의 저온균열 저항성을 평가 할 수 있는 기법이 요구된다. 본 연구의 목적은 용착금속의 저온균열 저항성을 평가하는 것인데, 저온균열 저항성은 용착금속의 미세조직에 따라 다르게 나타날 수 있다. 용착금속의 합금조성은 기본적으로 용착금속에 요구되는 최저 강도와 충격인성을 만족할 수 있도록 설계한다. 하지만 유사한 강도의 유사한 합금조성이더라도 일부 합금 성분에 의해 용착금속의 미세조직들은 상이하게 나타날 수 있는데, 미세조직 특성에 의하여 용착금속의 강도와 저온인성이 결정된다. 용착금속의 저온균열 저항성을 평가하기위하여 Gapped Bead-on-Groove(G-BOG) 시험에 사용된 모재는 50mm 두께의 mild steel을 사용하였으며, 모재의 희석을 방지하기위해 15mm 깊이로 V-groove 가공 후 buttering 용접 하였다. 용접된 시편은 다시 5mm 깊이로 V-groove로 2차 가공 후 Ar + 20% $Co_2$ gas를 사용하여 용접하였다. 용접재료는 ER-100S-G grade로 비슷한 합금조성을 갖는 2 종류를 사용하였다. A용접재료는 Ti 이 0.1% 함유 되었으며, B용접재료는 Ti 함유되지 않은 것을 사용하였다. 또한 예열 온도에 따라 저온균열 감수성을 평가하기위하여 모재의 예열온도를 각각 상온, $50^{\circ}C,\;75^{\circ}C,\;100^{\circ}C$로 하여 실험을 진행하였다. 용착금속의 미세조직을 확인해본 결과 Ti 함유된 A 용착금속 미세조직은 대부분 침상형페라이트로 나타났으며, Ti 함유되지 않은 B 용착금속 미세조직은 대부분 베이나이트로 나타났다. G-BOG 시험 결과 Ti 함유된 A 시편이 Ti 함유되지 않은 B 시편보다 저온균열 발생량이 적었다. 이는 용착금속의 미세조직분포 및 특성에 따라 저온균열감수성이 다르다는 것을 나타낸다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.50 no.1
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• pp.31-38
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• 2022

TR module using in satellite must consider discriminative electrical and mechanical requirements compare to the one using in ground and aircraft system since not only the environment level of vibration and shock during the launch stage but also the level of radiation, vacuum and thermal variation from orbit environment are more severe than atmosphere condition. This paper describes the environmental conditions of launch and the orbit and, suggests design method of TR module applying GaN to satisfy the unique environmental requirements of satellite systems by especially focusing on parts selection, derating design, RF budget design, manufacturing process design, and thermal design of TR module.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.2
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• pp.153-160
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• 2010

A magnetocardiogram (MCG) is a recording of the biomagnetic signals generated by cardiac electrical activity. Biomagnetic instruments are based on superconducting quantum interference devices (SQUIDs). A liquid cryogenic Dewar flask was used to maintain the superconductors in a superconducting state at a very low temperature (4 K). In this study, the temperature distribution characteristics of the liquid helium in the Dewar flask was investigated. The Dewar flask used in this study has a 30 L liquid helium capacity with a hold time of 5 d. The Dewar flask has two thermal shields rated at 150 and 40 K. The temperatures measured at the end of the thermal shield and calculated from the computer model were compared. This study attempted to minimize the heat transfer rate of the cryogenic Dewar flask using an optimization method about the geometric variable to find the characteristics for the design geometric variables in terms of the stress distribution of the Dewar flask. For thermal and optimization analysis of the structure, the finite element method code ANSYS 10 was used. The computer model used for the cryogenic Dewar flask was useful to predict the temperature distribution for the area less affected by the thermal radiation.