• Journal of KIISE
• /
• v.44 no.10
• /
• pp.1005-1018
• /
• 2017

Recently, virtualization has become an essential component of cloud computing due to its various strengths, including maximizing server resource utilization, easy-to-maintain software, and enhanced data protection. However, since virtualization allows sharing physical resources among the VMs, the system performance can be deteriorated due to device contentions. In this paper, we first investigate the I/O overhead based on the number of VMs on the same server platform and analyze the block I/O process of the KVM hypervisor. We also propose an in-memory block cache mechanism, called QBic, to overcome I/O virtualization latency. QBic is capable of monitoring the block I/O process of the hypervisor and stores the data with a high access frequency in the cache. As a result, QBic provides a fast response for VMs and reduces the I/O contention to physical devices. Finally, we present a performance measurement of QBic to verify its effectiveness.

• Journal of KIISE:Information Networking
• /
• v.30 no.2
• /
• pp.179-188
• /
• 2003

Advances in wireless networking technology has engendered a new paradigm of computing, called mobile computing, in which users carrying portable devices have access to a shared infrastructure independent of their physical locations. Wireless communication has some restraints such as disconnection, low bandwidth, a variation of available bandwidth, network heterogeneity, security risk, small storage, and low power. Power adaptation routing scheme overcome the shortage of power by adjusting the output power, was proposed. Existing power saving routing algorithm has some minor effect such as seceding from shortest path to minimize the power consumption, and number of nodes that Participate in routing than optimal because it select a next node with considering only consuming power. This paper supplements the weak point in the existing power saving routing algorithm as considering the gradual approach to final destination and the number of optimal nodes that participate in routing.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.7A
• /
• pp.547-556
• /
• 2003

This paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for low-area elliptic curve cryptographic processor. The proposed arithmetic unit, which is linear feed back shift register (LFSR) architecture, is designed by using hardware sharing between the binary GCD algorithm and the most significant bit (MSB)-first multiplication scheme, and it can perform both division and multiplication in GF(2$^{m}$ ). In other word, the proposed architecture produce division results at a rate of one per 2m-1 clock cycles in division mode and multiplication results at a rate of one per m clock cycles in multiplication mode. Analysis shows that the computational delay time of the proposed architecture, for division, is less than previously proposed dividers with reduced transistor counts. In addition, since the proposed arithmetic unit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed novel architecture can be used for both division and multiplication circuit of elliptic curve cryptographic processor. Specially, it is well suited to low-area applications such as smart cards and hand held devices.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.1 s.343
• /
• pp.79-84
• /
• 2006

This paper proposed a novel H.264 deblocking filter for low-power mobile multimedia SoCs. In H.264 deblocking filter, filtering can be skipped on some pixels when pixel value differences satisfy some specific conditions. Furthermore, whole filtering can be skipped when quantization parameter is less than 16. Based on these features, power consumption can be significantly reduced by shutting down deblocking filter partially or as a whole. The proposed deblocking filter can shut down partial or whole blocks with simple control circuits. Common hardware performs both horizontal filtering and vertical filtering. It was implemented in silicon chip using $0.35{\mu}m$ standard cell library technology. The gate count is about 20,000 gates. The maximum operation frequency is 108MHz. The maximum throughput is 30 frame/s with CCIR601 image format.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.1
• /
• pp.8-15
• /
• 2007

This paper proposed hardware architecture of the block cryptographic algorithm HIGHT aiming small size and low power application, and analyzed its performance. The HIGHT is a modified algorithm of the Feistel. The encryption and decryption circuit were designed as one iterative block. It reduces the redundant circuit that yields small area. For the performance improvement, the circuit generates 32-bit subkey during 1 clock cycle. we synthesized the HIGHT with Hynix $0.25-{\mu}m$ CMOS technology. The proposed circuit size was 2.658 EG(equivalent gate), and its power consumption was $10.88{\mu}W$ at 2.5V for 100kHz. It is useful for a passive RFID tag or a smart IC card of a small size and low power.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.5
• /
• pp.11-19
• /
• 2014

In this paper, a low complexity parallel sphere decoder algorithm is proposed for high-order MIMO system. It reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by static tree-pruning and dynamic tree-pruning using scalable node operators, and offers near-maximum likelihood decoding performance. Moreover, it also offers hardware-friendly node operation algorithm through fixing the variable computational complexity caused by the sequential nature of the conventional SD algorithm. A Monte Carlo simulation shows our proposed algorithm decreases the average number of expanded nodes by 55% with only 6.3% increase of the normalized decoding time compared to a full parallelized FSD algorithm for high-order MIMO communication system with 16 QAM modulation.

• Journal of Digital Contents Society
• /
• v.18 no.1
• /
• pp.159-165
• /
• 2017

In order to solve problems in automatic quality inspection of tablet capsules, computation-efficient image processing technique, appropriate threshold setting, edge detection and segmentation methods are required. And since existing automatic system for quality inspection of tablet capsules is of very high cost, it needs to be reduced through the realization of low-price hardware system. This study suggests a technique that uses low-cost camera module to obtain image and inspects dents on tablet capsules and sorting them by applying TLS curve fitting technique and edge-based image segmentation. In order to assess the performance, the major classifications algorithm of PCA, ICA and SVM are used to evaluate training time, test time and accuracy for capsule image area and curve fitting edge data sets.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.43 no.3 s.309
• /
• pp.92-99
• /
• 2006

In this paper, a low-power deblocking filter structure for H.264 video coding algorithm is proposed. By sharing addition hardware for common filter coefficients, we have designed an efficient deblocking filter structure. Proposed deblocking filter utilizes MUX and DEMUX circuits for input data sharing and shows 44.2% reduction for add operation. In the HDL coding simulation and FPGA implementation, we achieved 19.5% and 19.4% gate count reduction, respectively, comparison with the conventional deblocking filter structure. Due to its efficient processing scheme, the proposed structure can be widely used in H.264 encoding and decoding SoC.

• KIPS Transactions on Computer and Communication Systems
• /
• v.4 no.1
• /
• pp.11-14
• /
• 2015

WSN (Wireless Sensor Network) based on low-power is one of the core technologies in the ubiquitous society. In this paper, we present a border surveillance and control system in WSN environment. The system consists of static sensor node, mobile sensor node, static gateway, mobile gateway, server and mobile application. Mobile applications are divided into user mode and manager mode. So users monitor border surveillance through mobile phone and get information of border network environment without time and space constraints. In manager mode, for the flexible operation of nodes, manager can update to the software remotely and adjust the position of the mobile node. And also we implement a suitable multi-hop routing protocol for scalable low-power sensor nodes and confirm that the system operates well in WSN environment.

• The Journal of the Korea Contents Association
• /
• v.7 no.6
• /
• pp.69-78
• /
• 2007

In recent years, embedded mobile systems have been expanding their application domains from embedded portable devices which only execute a specialized application such as MP3 player or digital camcoder to digital convergence devices which execute more complicated applications converged various functionalities such as video and audio play, digital dictionary, DMB, games, phone, etc. As it requires the increasing hardware performance such as more faster CPU and more larger RAM, display, disk size, it has brought about a corresponding increase in power consumption. However, coupled with relatively small gains in battery capacity over recent years, the importance of software architecture including intelligent power management has become paramount. In this paper, we have ported UbiFOSTM with energy saving techniques on the ARM9-based MBA2440 platform. For energy savings, we adapted the dynamic power management and the device power management schemes based on monitoring workload. Experimental results with some well-known applications show that proposed low power technique could save energy up to 24 %.