• Journal of KIISE:Software and Applications
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• v.35 no.9
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• pp.554-561
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• 2008

Prediction technique of user's intention can be used as a post-processing method for reducing the search space of an automatic speech recognizer. Prediction technique of system's intention can be used as a pre-processing method for generating a flexible sentence. To satisfy these practical needs, we propose a statistical model to predict speakers' intentions that are generalized into pairs of a speech act and a concept sequence. Contrary to the previous model using simple n-gram statistic of speech acts, the proposed model represents a dialogue history of a current utterance to a feature set with various linguistic levels (i.e. n-grams of speech act and a concept sequence pairs, clue words, and state information of a domain frame). Then, the proposed model predicts the intention of the next utterance by using the feature set as inputs of CRFs (Conditional Random Fields). In the experiment in a schedule management domain, The proposed model showed the precision of 76.25% on prediction of user's speech act and the precision of 64.21% on prediction of user's concept sequence. The proposed model also showed the precision of 88.11% on prediction of system's speech act and the Precision of 87.19% on prediction of system's concept sequence. In addition, the proposed model showed 29.32% higher average precision than the previous model.

• Journal of Broadcast Engineering
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• v.3 no.1
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• pp.69-84
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• 1998

In digital broadcasting, services such as digital satellite TV, cable TV and digital terrestrial TV, several video programs are compressed by MPEG-2, and then simultaneously transmitted over a conventional CBR (Constant Bit Rate) broadcasting channel. In this paper, we propose a joint quality control scheme to be able to accurately control the relative picture quality among the video programs, which is achieved by simdt;,nL'Ously controlling the video encoders to generate the VBR (Variable Bit Rate) compressed video streams. Our quality control scheme can prevent the video buffer overflow and underflow by total target bit allocation process, and also exactly control the relative picture quality in terms of PSNR (Peak Signal to Noise Ratio) between some programs requiring higher picture quality and others by rate-distortion modification. Furthermore we present a rate-distortion estimation method for MPEG-2 video, which is base of our joint quality control, and verify its performance by experiments. The most attractive features of this estimation method are as follows: 1) computational complexity is low because main operation for the estimation is to calculate the histogram of OCT coefficients into quantizer; 2) estimation results are very accurate enough to be applied to the practical MPEG-2 video coding applications. Simulation results show that the proposed joint quality control scheme accurately controls the relative picture quality among the video progran1s transmitted over a single channel as well as provides more consistent and higher picture quality than independent coding scheme that encodes each program independently.

• The Journal of the Korea Contents Association
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• v.7 no.4
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• pp.234-240
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• 2007

The purpose of this paper was to architecture optimal model of the scooped swing in high bar. The scooped swing was modeled to the double pendulum and was simulated with the Lagrange's equation of motion. Lagrange's method based on a energy approaching method was implemented as a equation of motion. The subject was a national man-gymnast(age 18yrs, height 153 cut mass 48 kg) and the high bar of SPIETH company was used to measure the scooped swing. Qualisys system(six MCU-240 cameras, QTM software)was used to capture data for imaging analysis. The solution of a model and data processing were solved in Mathematica5.0. The results were as follows: First model value of maximum bar displacement was longer than experimental value, that is, 0.02 m. Second, both angular pattern of segment1(HAT) had a increasing curve but curve patterns had a different concave and convex me. Third the experimental value of maximum angular angle of segment2(total leg) had larger than model value, that is, $4^{\circ}$. Conclusively, model parameters were quasi-optimized to obtain a quasi-match between simulated and actual performances. It hopes to simulate a human model by means of integrating musculoskeletal and neuromuscular system in the future study.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.12
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• pp.5843-5848
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• 2011

To improve the efficiency of the channel spectrum and to reduce the power consumption of the system in EVRC, the voice signal is compressed and transmitted only when the user speaks to. In addition to this, voice frames are divided into three rates 1, 1/2 and 1/8 and each frame is handled differently. For example, we assumed that the input is silence region if the 1/8 rate is used. In this paper, the sections are firstly separated into the voiced speech signal region, unvoiced speech signal region, and silence region by using distribution characteristics of LSP parameters. Then the paper suggested to encode 1 rate for the voiced speech signal, 1/2 rate for the unvoiced speech signal region, 1/8 rate for the silence region. In other words, traditional way of transmission is used when sending full rate in the EVRC. However, when sending half rate, the voice is firstly distinguished between voiced and unvoiced. If the voice is distinguished as voiced, voice is converted into full rate before the transmission. If it is distinguished as silence, EVRC's basic rate is applied. In the experimental results with SNR, ASDM, transmission bit rate measurement, we have demonstrated that voice quality was improved by using the proposed algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.9
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• pp.514-526
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• 2004

Microarray is a new technique for gene expression experiment, which has gained biologist's attention for recent years. This technology enables us to obtain hundreds and thousands of expression of gene or genotype at once using microarray Since it requires manual work to analyze patterns of gene expression, we want to develop an effective and automated tools to analyze microarray image. However it is difficult to analyze DNA chip images automatically due to several problems such as the variation of spot position, the irregularity of spot shape and size, and sample contamination. Especially, one of the most difficult problems in microarray analysis is the block and spot addressing, which is performed by manual or semi automated work in all the commercial tools. In this paper we propose a new algorithm to address the position of spot and block using a new concept of regular structure grid searching. In our algorithm, first we construct maximal I-regular sequences from the set of input points. Secondly we calculate the rotational angle and unit distance. Finally, we construct I-regularity graph by allowing pseudo points and then we compute the spot/block address using this graph. Experiment results showed that our algorithm is highly robust and reliable. Supplement information is available on http://jade.cs.pusan.ac.kr/~autogrid.

• Journal of Korea Multimedia Society
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• v.10 no.8
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• pp.1068-1077
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• 2007

This paper proposes a method that extracts characteristics of cracks such as length, thickness and direction from a concrete slab surface image with image processing techniques. These techniques extract the cracks from the concrete surface image in variable conditions including bad image conditions) using the ART2-based RBF network to recognize the dominant directions -45 degree, 45 degree, horizontal and vertical) of the extracted cracks from the automatically calculated specifications like the lengths, directions and widths of the cracks. Our proposed extraction algorithms and analysis of the concrete cracks used a Robert operation to emphasize the cracks, and a Multiple operation to increase the difference in brightness between the cracks and background. After these treatments, the cracks can be extracted from the image by using an iterated binarization technique. Noise reduction techniques are used three separate times on this binarized image, and the specifications of the cracks are extracted form this noiseless image. The dominant directions can be recognized by using the ART2-based RBF network. In this method, the ART2 is used between the input layer and the middle layer to learn, and the Delta learning method is used between the middle layer and the output layer. The experiments using real concrete images showed that the cracks were effectively extracted, and the Proposed ART2-based RBF network effectively recognized the directions of the extracted cracks.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.2
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• pp.141-154
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• 2002

More efforts have been given to solve the problems related to computer software by process assessment. ISO/IEC 15504(SPICE) has been developed as standardized means for process assessment. The purpose of this paper is to design and implement a process assessment system which is appropriated to the Korean assessment environment based on ISO/IEC 15504. Referring documents are: IS0/1EC 15504 standardized documents, the assessment provisions of the SPICE committee in Korea, and research papers applied the existing process assessment system to real cases. Among a lot of processes, this system is designed for (ENG2). The proposed system in the paper will support the whole process of assessment, presenting the goals and end-products for each assessment step and making it possible to compose and save the product on the same screen. In determining process rating, assessors can retrieve the saved data and documents. By doing so, the system will improve reliability in process rating. The proposed system includes 7 steps of pre-assessment and 9 steps of actual assessment in order to fully prepare assessors for process assessment. And each step has been standardized to improve user-friendliness. This system is designed to provide assessors with specific details of standardized documents, the goals of the process, outcomes of implementing the process, and presentations of base practices and input/output products. Above all, the system automatically generates an assessment rating, by calculating based on input data which assessors make out. It also presents outcomes graphically.

• Korean Security Journal
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• no.12
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• pp.177-200
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• 2006

This research result that analysis as following. First, difference that keep in mind partially as result that verify difference of job-stress by demography special qualitys that is common people guard's society and turnover intention appeared. Second, result that analyze relation with job-stress and turnover intention, displayed statical correlation in job environment. Third, result that keep in mind as statistical as result that verify effect that common people guard's job-stress gets to turnover intention appeared. During is job-stress variable, was expose that exert effect that keep in mind to turnover intention job surrounding and job special quality. Suggestion point through this research as following be. To raise common people guard's job-stress and turnover intention. system improvement strategy about social estimation etc.. is effective, and do on the basis of this and may have to establish common people guard's enhancing morale plan strategy, low complement that can exert negative impact in change of post for example, line of duty that it is seldom competence, daytime that can elicit common people guards' job satisfaction. Is in visual point that activation of continuous research is leaned against by depth interview and review through qualitative research was insufficient relatively in virtue research so far in research after.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.