• Title, Summary, Keyword: 인쇄회로기판

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Pad data extraction method for PCB by image Scanner (이미지스캐너를 사용한 인쇄회로기판의 패드추출 방법)

  • 정진회;박태형
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • pp.571-575
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    • 2004
  • 인쇄회로기판(PCB)을 조립 또는 검사하는 장비의 작업 프로그램 작성을 위해서는, 납땜 패드의 위치와 크기에 대한 데이터가 필요하다. CAD 파일, 거버 파일 등을 사용하여 패드를 추출하는 방법이 많이 사용되고 있으나, 본 논문은 이미지 스캐너를 사용하여 추출하는 방법을 새로이 제안한다. 제안된 방법은 통계적 영상 처리를 적용하여, 기존의 일반적인 영상처리 방식보다 기판 별 패드 색상의 차이에 강인하다. 실제 PCB 에 대한 실험을 통하여 제안 방법의 성능을 검증한다. 제시된 방법은, CAD 파일과 거버 파일의 확보가 어려운 임가공 업체 등의 생산현장에서 사용될 수 있다.

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A Design of a High-Speed Multilayer Printed Circuit Board though signal Verification (신호 검증을 통한 고속 다층 인쇄회로기판의 설계)

  • Choe, Cheol-Yong
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.1
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    • pp.249-257
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    • 1998
  • 다층 인쇄회로기판에서 고속 신호를 정확하고 신속하게 배선 설계하려면, 물리적 설계 규칙과 신호 잡음을 고려한 전기적 설계 규칙을 정립하고, 적용할 신호 검증 도구를 사용하여 신호의 충실성을 검증하여야 한다. 본 논문은 현재 개발 제작되어 동작 중에 있는 HIPSS(High Performance Storage System)보드에 대한 전기적 설계 규칙과 고속 신호의 배선에 따른 일부 고속 신호의 신호 검증 방법을 설명한다. 또한 전기적 설계 규칙을 적용하여 인쇄회로기판을 설계하는 경우, 발생하는 신호 지연, 반사 그리고 누화 등의 신호 잡음을 검증 도구를 이용하여 시뮬레이션 하고, 분석한 결과를 보이며, 수정된 고속 신호의 배선 설계를 확인한다.

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Trend of Surface Treatment for Printed Circuit Board (인쇄회로기판의 표면처리 기술동향)

  • Kim, Yu-Sang
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • pp.203-203
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    • 2011
  • 최근 전자, 정보통신기기의 고기능, 고속화, 소형화, 경량화 요구에 따라 반도체 소자인 LSI와 함께 인쇄회로기판도 해가 갈수록 고밀도, 고다층화, 얇고 균일한 도금과 함께 밀착성향상 추세로 급속하게 진행되고 있다. 인쇄회로기판에서 표면처리는 매우 광범위하고 많은 문제점이 있지만 고주파노이즈감소를 위하여 도금두께 균일화 평활면의 접착, 파인패턴 형성과 절연성이 가장 중요하다.

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8-Layer System-in-Board Embedded Printed Circuit Board for Area Reduction of RF Communication System (RF 통신 시스템의 면적 축소를 위한 8층 시스템-인-보드 임베디드 인쇄회로기판)

  • Jeong, Jin-Woo;Yi, Jae-Hoon;Chun, Kuk-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.2
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    • pp.67-72
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    • 2011
  • 8-layer printed circuit board is designed and implemented for triple band(2.3/2.5/3.5GHz) m-WiMAX system. In order to maintain excellent RF performance, low dielectric constant material is used for implementation of the printed circuit board. Also, embedded printed circuit board which embed passive devices is manufactured to reduce total system area. As a result, total system area is cut off by 9%. Triple band m-WiMAX system is produced using embedded printed circuit board. Furthermore, internet connecting test is performed and proved successful running of the system. The developed embedded printed circuit board will provide a effective solution for system area reduction and low loss signal RF communication system.

Physical Property Changes of Wasted Printed Circuit Board by Heat Treatment (열처리에 의한 폐 인쇄회로기판의 물성변화)

  • Kim, Boram;Park, Seungsoo;Kim, Byeongwoo;Park, Jaikoo
    • Resources Recycling
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    • v.27 no.1
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    • pp.55-63
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    • 2018
  • Physical property changes of printed circuit board (PCB) according to heat treatment conditions were investigated. The heat treatment was carried out in air and nitrogen atmosphere at temperature range from $200^{\circ}C$ to $325^{\circ}C$. Thermogravimetric analysis showed that the PCB was pyrolyzed in two steps. The thickness of PCB expanded by 11~28% at about $300^{\circ}C$ in both air and nitrogen atmosphere as layer disintegration occurred. Mechanical strength of PCB decreased from 338.4 MPa to 20.3~40.2 MPa due to the delamination caused by the heat treatment. The heated printed circuit boards were crushed and sieved for analysis of density distribution and liberation degree of copper according to particle size. As a result of the density distribution measurement, non metallic particles and copper particles were concentrated into different size range, respectively. The liberation degree of copper was improved from 9.3% to 100% at size range of $1,400{\sim}2,000{\mu}m$ by heat treatment.

Development of Build up Multilayer Board Rapid Manufacturing Process Using Screen Printing Technology (스크린인쇄 법을 이용한 Build-up다층인쇄회로기판의 쾌속제조공정 기술개발)

  • 조병희;정해도;정해원
    • Journal of the Microelectronics and Packaging Society
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    • v.6 no.4
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    • pp.15-22
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    • 1999
  • Generally, many equipments and a long lead time ale required to manufacture the build-up multilayer board through various processes such as etching, plating, drilling etc. Wet process is suitable for mass production, however it is not adequate for manufacturing prototype in developing stage. In this study, a silk screen printing technology is introduced to make a prototype build-up multilayer board. As for the material photo/thermal curable resin and conductive paste are used for forming dielectric and conductor. And conductive paste fills vias for interconnecting each layer, and also is used for circuit patterning by silk screen technology. Finally, the basic concept and the possibility of build-up multilayer board prototype is proposed and verified as a powerful approach, compared with the conventional processes.

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Recovery of Waste Back Board and Gold from the Process of Printed Circuit Board (인쇄회로기판(印刷回路基板) 제조공정(製造工程)의 폐(廢) Back Board 및 금(金) 회수(回收))

  • Kim, Yu-Sang
    • Resources Recycling
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    • v.19 no.1
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    • pp.57-65
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    • 2010
  • Recently, we have investigated the recovery of resources from the waste material of manufacturing printed circuit board. As printed circuit board or chip has become light, small, high reliability, it is necessary to reuse and recover resources from them. Especially, the printed circuit board that has been used for important mobile electronic pans are plated with min.0.03 ${\mu}m$ to max.50 ${\mu}m$. As increasing the cost of gold, raw material, chemicals, payments and waste material, it has been accelerated the competition for reuse and recovery. But, it is insufficiency of technician and equipments for the recovery of effective resource. In this paper, as analyzing the technical trend of gold recovery and waste back board from the manufacturing process of printed circuit board, it may be effective of recycling, further more it may be contributed to develop the valuable resources.

Investigation of Power Bus Decoupling by the Screw Connection of the PCB to Chassis (나사를 이용한 기구물과 인쇄회로기판 연결이 전원단 잡음 감소에 미치는 영향 분석)

  • 권덕규;이신영;이해영;이재욱;배승민
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.10
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    • pp.1040-1047
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    • 2002
  • In this paper, we investigated noise decoupling on the power bus by the screw connection, used to the mechanical join and grounding of the PCB ground to chassis. The screw connection penetrates the power bus and then it affects noise propagation on the power bus. To verify effect of the screw connection, we compare bare board with board having screws connection with 0.5 mm separation between power bus and chassis. From these results, we observed that the power bus noise was decreased about 5 dB at the frequency range from 0.1 GHz to 1 GHz. Also, we verified that a 4-layer PCB with signal trace had the better signal quality up to 600 MHz by the screw connection. Therefore, these results will be useful in designing to the high speed circuit and chassis.

Applications and Technical Trends of Electroplating Copper Foil (전해동박의 적용 사례 및 기술 동향)

  • Kim, Seung-Min;Jeon, Sang-Hyeon;Jo, Gwang-Cheol;An, Jung-Gyu
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • pp.59-61
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    • 2015
  • 본고에서는 전해동박의 개발 연혁, 제조 공정 및 주요 적용 사례에 대해 소개한다. 전해동박이 전자 소재에 적용되는 대표적인 사례는 Li 이차전지의 음극 집전체 및 인쇄회로기판의 회로이다. Mobile Device의 슬림화 및 다기능화에 따라 Li 이차전지의 용량 증대 및 인쇄회로기판의 협피치화가 필요하다. 따라서 Li 이차전지의 단위 부피당 용량 증대를 위해서는 음극 집전체로 적용되는 동박은 극박화 및 고강도 특성이 요구되고 있다. 인쇄회로기판의 협피치화에 따라 이들 제품에 적용되고 있는 동박은 두께 및 조도를 저감시키는 방향으로 기술이 전개되고 있다. 본고에서는 전자 소재용으로 적용되고 있는 전해 동박의 최근 제품 및 기술 동향과 향후 제품 전개 방향에 대해 논의하고자 한다.

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Thermo-mechanical Behavior Characteristic Analysis of $B^2it$(Buried Bump Interconnection Technology) in PCB(Printed Circuit Board) (인쇄회로기판 $B^2it$(Buried Bump Interconnection Technology) 구조의 열적-기계적 거동특성 해석)

  • Cho, Seung-Hyun;Chang, Tae-Eun
    • Journal of the Microelectronics and Packaging Society
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    • v.16 no.2
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    • pp.43-50
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    • 2009
  • Although thin PCBs(Printed Circuit Boards) have recently been required for high density interconnection, high electrical performance, and low manufacturing cost, the utilization of thin PCBs is severely limited by warpage and reliability issues. Warpage of the thin PCB leads to failure in solder-joints and chip. The $B^2it$(Buried Bump Interconnection Technology) for PCB has been developed to achieve a competitive manufacturing price. In this study, chip temperature, package warpage, chip stress and solder-joints stress characteristics of the PCB prepared with $B^2it$ process have been calculated using thermo-mechanical coupled analysis by the FEM(Finite Element Method). FEM computation was carried out with the variations in bump shapes and kinds of materials under 1.5W power of chip and constant convection heat transfer. The results show that chip temperature distribution reached more quickly steady-state status with PCB prepared with $B^2it$ process than PCB prepared with conventional via interconnection structure. Although $B^2it$ structures are effective on low package warpage and chip stress, with high strength bump materials arc disadvantage for low stress of solder-joints. Therefore, it is recommended that optimized bump shapes and materials in PCB design should be considered in terms of reliability characteristics in the packaging level.

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