• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.567-572
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• 2019

In this paper, we propose an algorithm to perform convolution, pooling, and ReLU operations in CNN using binary image and binary kernel. It decomposes 256 gray-scale images into 8 bit planes and uses a binary kernel consisting of -1 and 1. The convolution operation of binary image and binary kernel is performed by addition and subtraction. Logically, it is a binary operation algorithm using the XNOR and comparator. ReLU and pooling operations are performed by using XNOR and OR logic operations, respectively. Through the experiments to verify the usefulness of the proposed algorithm, We confirm that the CNN operation can be performed by converting it to binary logic operation. It is an algorithm that can implement deep running even in a system with weak computing power. It can be applied to a variety of embedded systems such as smart phones, intelligent CCTV, IoT system, and autonomous car.

• Proceedings of the Korea Contents Association Conference
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• 2014.11a
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• pp.293-294
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• 2014

정보 검색 분야에서 키 탐색을 빠르게 하기 위한 인덱스 구조로 이진 트라이가 대표적으로 사용된다. CB 트리는 이진 트라이 구조를 구현할 경우 발생하는 저장 공간의 부담을 축소하기 위해 이진 시퀀스를 사용하여 저장한다. 이는 저장 공간 측면에서 상당한 우수성을 보여주나 키의 잦은 삽입 및 삭제 요구가 있을 경우 이진 비트열에 대한 시프트 연산이 요구되는 부담이 있다. 본 논문에서는 완전 이진 트라이 구조를 사용하여 CB 트리를 표현하는 방법을 제시하였다. 저장 공간의 크기가 증가되기는 하지만 키가 삽입되거나 삭제되어도 이진 비트열에 대한 시프트 연산이 필요하지 않은 장점이 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.168-170
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• 2011

본 논문에서는 항공 갑판의 비파괴 검사 영상에서, 조직의 이상이나 결함의 정도를 검출하는 기존의 방법보다 결함 검출의 정확도를 개선한 방법을 제안한다. 제안된 결함 검출 방법은 결함의 윤곽선을 추출하기 위하여 라플라시안 필터링 기법을 적용하여 윤곽선을 추출한다. 라플라시안 필터링 기법을 적용하여 윤곽선을 추출할 경우에는 결함 이외의 다른 객체들의 윤곽선도 검출된다. 따라서 본 논문에서는 이진화 기법과 팽창 연산을 적용하여 결함의 후보 객체들을 연결한다. 그리고 Grassfire 라벨링 기법을 적용하여 잡음을 제거하고 팽창 연산과 침식 연산을 이용하여 결함 후보 영역의 크기를 조정한다. 크기가 조정된 결함 후보 영역을 기반으로 원 영상에서 결함 후보 영역을 추출한다. 결함 후보 영역에서 결함 영역을 추출하기 위해 결함 후보 영역의 명암 대비를 증가시키고 결함 후보 영역의 주변 정보를 이용하여 이진화한다. 이진화 된 영역에서 Grassfire 라벨링 기법을 이용하여 잡음을 제거하고 최종적으로 결함 영역을 검출한다. 본 논문에서 제안한 방법으로 항공갑판의 결함을 추출한 결과, 기존의 방법보다 항공 갑판의 결함을 추출하는데 효과적인 것을 확인하였다.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.4
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• pp.418-423
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• 2004

The motion estimation algorithm based block matching is a widely used in the international standards related to video compression, such as the MPEG series and H.26x series. Full search algorithm(FA) ones of this block matching algorithms is usually impractical because of the large number of computations required for large search region. Fast search algorithms and conventional binary block matching algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is less performance than full search algorithm. This paper presents new Boolean matching algorithm, called BCBM(Bit Converted Boolean Matching). Proposed algorithm has performance closed to the FA by Boolean only block matching that may be very efficiently implemented in hardware for real time video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.08㏈ loss than FA but is about 0.96∼2.02㏈ gain than fast search algorithm and conventional Boolean matching algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.771-777
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• 2012

This paper proposes a binary arithmetic encoder of CABAC using a Common Operation Unit including the three modes. The binary arithmetic encoder performing arithmetic encoding and renormalizer can be simply implemented into a hardware architecture since the COU is used regardless of the modes. The proposed binary arithmetic encoder of CABAC includes Context RAM, Context Updater, Common Operation Unit and Bit-Gen. The architecture consists of 4-stage pipeline operating one symbol for each clock cycle. The area of proposed binary arithmetic encoder of CABAC is reduced up to 47%, the performance of proposed binary arithmetic encoder of CABAC is 19% higher than the previous architecture.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.925-927
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• 2011

본 논문에서는 확장 이진 최대공약수 알고리듬 (Extended Binary GCD algorithm)을 기본으로 GF($2^m$) 상에서 유한체 나눗셈 연산을 위한 고속 알고리듬을 제안하고, 제안한 알고리듬을 기본으로 한 나눗셈 연산기의 FPGA 설계 구현에 관하여 기술한다. 제안한 알고리듬은 Verilog HDL 로 기술하였고, Xilinx FPGA virtex4-xc4vlx15 디바이스를 타겟으로 하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7C
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• pp.946-953
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• 2004

Fast search and conventional boolean matching motion estimation algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is difficult of implementation of hardware because of high control overhead and that is less performance than Full search Algorithm(FA). This paper present new all binary block matching algorithm, called Bit Converted All Binary Block Matching(BC-ABBM). Proposed algorithm have performance closed to the FA by boolean only block matching that may be very efficiently implemented in hardware for low bit rate video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.04dB loss than FA but is about 0.6 ∼ 1.4dB gain than fast search algorithm and conventional boolean matching algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.11
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• pp.3087-3093
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• 2009

Digital filters are indispensible element in digital signal processing area. The performance of digital filter based on adding and multiplying operation, such as computational speed and power consuming is determined by the orders and coefficients of filter which has on effect area of semiconductor chip when it is implemented by VLSI technology. In this research, in order to performance improvement of digital filter, we proposed the algorithm to speed-up the operation of digital filter associated with the minimum signed digit representation of binary number system and method to simplify the digital filter design associated with common subexpression elimination. The performance of proposed method is evaluated by the computational speed and design-simplicity by experimental implemented digital filter on FPGA.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.126-131
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• 2004

Full search algorithm(FA) provides the best performance but this is usually impractical because of the large number of computations required for large search region. Fast search and conventional Boolean matching algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is difficult of implementation of hardware because of high control overhead and that is less performance than FA. This paper presents new Boolean matching algorithm, called BCBM(Bit Converted Boolean Matching). Proposed algorithm has performance closed to the FA by Boolean only block matching that may be very efficiently implemented in hardware for real time video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.08㏈ loss than FA but is about 0.96∼2.02㏈ gain than fast search algorithm and conventional Boolean matching algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.147-156
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• 1998

In this paper, an arithmetic processor using multi-valued logic is designed. For implementing of multi-valued logic circuits, we use current-mode CMOS circuits and design encoder which change binary voltage-mode signals to multi-valued current-mode signals and decoder which change results of arithmetic to binary voltage-mode signals. To reduce the number of partial product we use 4-radix SD number partial product generation algorithm that is an extension of the modified Booth's algorithm. We demonstrate the effectiveness of the proposed arithmetic circuits through SPICE simulation and Hardware emulation using FPGA chip.