• Journal of the Korean Solar Energy Society
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• v.32 no.spc3
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• pp.235-244
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• 2012

This paper presents a design and simulation of bi-directional DC/DC boost converter for a fuel cell system. In this paper, we analyze the equivalent model of both a boost converter and a buck converter. Also we propose the controller of bi-directional DC-DC converter, which has buck mode of charging a capacitor and boost mode of discharging a capacitor. In order to design a controller, we draw bode plots of the control-to-output transfer function using specific parameters and incorporate proper compensator in a closed loop. As a result, it has increased PM(Phase Margin) for better dynamic performance. The proposed bi-directional DC-DC converter's 3pole-2zero compensation method has been verified with computer simulation and simulation results obtained demonstrates the validity of the proposed control scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.