• Convergence Security Journal
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• v.16 no.7
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• pp.85-91
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• 2016

Block cipher is one of the prominent and important elements in cryptographic systems and study on the minimal construction is a major theme in the cryptographic research. Even and Mansour motivated by the study suggested a kind of block cipher called the Even-Mansour scheme in the early 1990s. It is a very simple cipher with one permutation and two secret keys. There have been many studies on the Even-Mansour scheme and security analysis of the scheme. We explain the Even-Mansour scheme and simplify those attacks on the Even-Mansour scheme with mathematical language. Additionally, we show that Pollard's rho attack to the discrete logarithm problem can be used to attack the Even-Mansour scheme with the same complexity of the Pollard's rho attack.

• Transactions of the Korean Society of Automotive Engineers
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• v.11 no.3
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• pp.115-123
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• 2003

With the advent of high performance computers and more efficient numerical algorithms, computational fluid dynamics(CFD) has come out as a modem alternative for reducing the use of wind tunnels test in automotive engineering. However, in spite of the fact that many competent researchers have made all their talents in developing turbulence model over since the past dozen or more years, it has been an important impediment in using the CFD effectively to design machinery and to diagnose or to improve engineering problems in the industry since the turbulence model has been acting as the Achilles' tendon in aspect of the reliability even to this time. In this study, Reynolds-averaged Wavier-Stokes equations were solved to simulate an incompressible turbulent flow around a bus-like bluff body near ground plane. In order to investigate the effect of the discretisation schemes and turbulence model on the aerodynamic forces several turbulence models with five convective difference schemes are adopted. From the results of this study, it is clear that choice of turbulence model and discretisation scheme profoundly affects the computational outcome. The results also show that the adoption of RNG $k-\varepsilon$ turbulence model and nonlinear quadratic turbulence model with the second order accurate discretisation scheme predicts fairly well the aerodynamic coefficients.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1C
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• pp.14-21
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• 2011

Cryptographic protocols based on bilinear pairings provide excellent alternatives to conventional elliptic curve cryptosystems based on discrete logarithm problems. Through active research has been done toward fast computation of the bilinear pairings, it is still believed that the computational cost of one pairing computation is heavier than the cost of one ECC scalar multiplication. However, there have been many progresses in pairing computations over binary fields. In this paper, we compare the cost of BLS signature scheme with ECDSA with equvalent level of security parameters. Analysis shows that the cost of the pairing computation is quite comparable to the cost of ECC scalar multiplication for the case of binary fields.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.