• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.2 s.105
• /
• pp.95-100
• /
• 2006

In this paper, we designed amplitude equalizer which is composed of amplifier, complementary shaping filter and attenuator in order to improve flatness of high order bandpass filter. We modified Chebyshev polynomial and calculated the prototype elements for complementary shaping filters by network synthesis. The amplitude equalizer is realized that it connects the 4th order complementary shaping filter designed by using calculated the prototype elements to the amplifier compensating for insertion loss and improving return loss, and with the attenuator for gain control. Using proposed amplitude equalizer, We certificated improvement in flatness of 13th order bandpass filter at WiBro band.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.11
• /
• pp.130-137
• /
• 2013

This paper presents analog front-end(AFE) circuits for bio-potential measurement. The proposed AFE is composed of IA(instrument amplifier), BPF(band-pass filter), VGA(variable gain amplifier) and SAR(successive approximation register) type ADC. The low gm(LGM) circuits with current division technique and Miller capacitance with high gain amplifier enable IA to implement on-chip AC-coupling without external passive components. Spilt capacitor array with capacitor division technique and asynchronous control make the 12-b ADC with low power consumption and small die area. The total current consumption of proposed AFE is 6.3uA at 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.111-117
• /
• 2006

Reconfigurable CMOS low-noise amplifier (LAN) has been developed for multi-mode/multi-band wireless receiver. By employing common-gate input stage, the performance can be optimized for multiple operation bands by simply controlling the output load impedance. Although the conventional common-gate LAN has larger than 3dB noise figure (NF), the newly developed negative feedback scheme enables the common-gate input LNA to have less than 2dB NF. To have optimum linearity performance of wireless receiver, the gain of the LNA can be controlled. The LNA implemented in a 0.13mm CMOS technology shows $19{\sim}20dB$ voltage gain, $1.7{\sim}2.0dB$ NF, -2dBm iIP3 at $1.8{\sim}2.5GHz$ frequency range. The LNA dissipates 7mW from a 1.2V supply voltage.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.23 no.5
• /
• pp.109-114
• /
• 2023

In this paper, a 2-channel Image-Reject receiver using a 65-nm CMOS process is presented for Ka-band compact radars. The designed receiver consists of Low-Noise Amplifier (LNA), IQ mixer, and Analog Baseband (ABB). ABB includes a complex filter in order to suppress unwanted images, and the variable gain amplifiers (VGAs) in RF block and ABB have gain tuning range from 4.5-56 dB for wide dynamic range. The gain of the receiver is controlled by on-chip SPI controllers. The receiver has noise figure of <15 dB, OP1dB of >4 dBm, image rejection ratio of >30 dB, and channel isolation of >45 dB at the voltage gain of 36 dB, in the Ka-band target frequency. The receiver consumes 420 mA at 1.2 V supply with die area of 4000×1600 ㎛.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.12
• /
• pp.40-48
• /
• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.12
• /
• pp.91-96
• /
• 2011

In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.

• Journal of Navigation and Port Research
• /
• v.27 no.1
• /
• pp.81-86
• /
• 2003

In the paper, the power amplifier using active biasing for LDMOS MRF-21060 is designed and fabricated. Driving amplifier using AH1 and parallel power amplifier AH11 is made to drive the LDMOS MRF 21060 power amplifier. The variation of current consumption in the fabricated 5 Watt power amplifier has an excellent characteristics of less than 0.1A, whereas passive biasing circuit dissipate more than 0.5A. The implemented power amplifier has the gain over 12 dB, the gain flatness of less than $\pm$0.09dB and input and output return loss of less than -19dB over the frequency range 2.11~2.17GHz. The DC operation point of this power amplifier at temperature variation from $0^{\circ}C$ to $60^{\circ}C$ is fixed by active circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.9
• /
• pp.673-684
• /
• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.7
• /
• pp.89-96
• /
• 2004

High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gain control are proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0㎃ to 300㎃ over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than 1.4% over the current range from 0A to 300㎃.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.45-51
• /
• 2009

A low-voltage, low-power analog CMOS front-end for a cardiac pacemaker is proposed. The circuits include a 4th order switched-capacitor (SC) filter with a passband of 80-120 Hz and a SC variable gain amplifier whose control range is from 0 to 24-dB with 0.094 dB step. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption, and correlated double sampling technique is used for reducing the finite gain effect of an inverter. The proposed circuit has been designed in a $0.35-{\mu}m$ CMOS process, and it achieves 80-dB SFDR at 5-kHz sampling frequency. The power consumption is only 330 nW at 1-V power supply.