• Proceedings of the Korean Information Science Society Conference
• /
• 2003.04d
• /
• pp.340-342
• /
• 2003

인터넷의 급격한 성장으로 요구되는 고속의 데이터 처리 능력과 시장의 급격한 변화에 빠르게 대응하기 위하여 기존의 범용 프로세서를 사용한 방법과 주문형 반도체를 이용한 네트워크 라우터/스위치 시스템의 단점을 보완하고, 두 방식의 장점만을 취합한 네트워크 프로세서가 개발되었다. 네트워크 프로세서는 네트워크 관련 기능에 특화된 구조를 채택하면서 프로그램이 가능하여 고속의 데이터 처리와 동시에 다양한 응용 프로그램의 개발을 가능하게 한다. 본 논문에서는 인텔사의 IXP1200 네트워크 프로세서를 이용하여 IPv4 라우터를 구현하여 네트워크 프로세서가 가지는 특징을 평가해 본다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2003.04d
• /
• pp.638-640
• /
• 2003

급변하는 네트워크 서비스에 대한 요구에 신속히 대응하고 새로운 특징에 대한 시스템의 수정과 보완이 용이하도록 고안된 것이 네트워크 프로세서이다. 본 논문은 네트워크 관련 응용에 특화된 인텔의 IXP1200 네트워크 프로세서를 이용하여 Differentiated Service를 위한 간단한 DiffServ Ingress Boundary Node로서의 Edge Router를 설계한다.

• The KIPS Transactions:PartA
• /
• v.13A no.4 s.101
• /
• pp.275-288
• /
• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2014.04a
• /
• pp.18-19
• /
• 2014

멀티프로세서 시스템 온칩 (MPSoC) 플랫폼은 고성능 임베디드 시스템을 위한 핵심 구성요소이다. MPSoC 를 구성하는 각각의 처리요소 (processing element, PE)는 대응하는 태스크의 연산 특징에 맞춤으로 최적화되어 있어야 한다. 갈수록 증가하는 고성능의 요구에 따라 동종 MPSoC 는 각각의 태스크 연산 특징에 최적화된 다양한 PE 를 보유한 이기종 MPSoC 로 발전되어 왔다. 따라서 이기종 MPSoC 의 코어들은 응용에 특화된 맞춤형 명령어 세트로 설계된다. 하지만 이러한 이기종성은 다양한 태스크로 구성된 응용들을 어떻게 서로 다른 특성을 지닌 PE 들에 매핑해야 최적의 시스템을 구성할 지를 결정해야 하는 부담을 컴파일러와 같은 툴에 지우고 있다. 잘못된 매핑은 시스템 성능을 현저히 저하시킬 소지가 있다. 본 연구에서는 멀티미디어 응용 태스크의 연산 패턴을 분석하여 최적의 태스크 매핑을 결정하는 기법을 제안하고 있다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.1
• /
• pp.123-130
• /
• 2016

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

• The KIPS Transactions:PartA
• /
• v.19A no.1
• /
• pp.45-50
• /
• 2012

The demand for faster execution time and lower energy consumption has compelled architects of embedded processors to customize it to the needs of their target applications. These processors consequently provide a rich set of specialized instructions in order to enable programmers to access these features. Such an instruction is typically a $multi$-$output$ $instruction$ (MOI), which outputs multiple results parallely in order to exploit inherent underlying hardware parallelism. Earlier study has exhibited that MOIs help to enhance performance in aspect of instruction counts and code size. However the earlier algorithm does not consider the register pressure. So, some selected MOIs introduce register spill/reload code that increases the code size and instruction count. To attack this problem, we introduce a novel iterated instruction selection algorithm based on the register pressure of each selected MOIs. The experimental results show the suggested algorithm achieves 3% code-size reduction and 2.7% speed-up on average.

• Journal of KIISE:Software and Applications
• /
• v.36 no.9
• /
• pp.758-766
• /
• 2009

In this days, the concept of time-to-market is important in embedded systems in consumer electronics. According to the short time of development period, it is also important in development of Software Development toolkits (SDKs). However, it is not improved to the development time of SDKs specialized in new processors. In this point, the Architecture Description Language (ADL) is an alternative to relieve the pain of building the SDKs as the required SDKs can be automatically generated from ADL for the processor. In this paper, we automatically generate SDKs specialized in processors using GNU Binutils. Through this research, we can more easier and faster produce the SDKs such as assembler and linker than by using handcrafted code.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2012.04a
• /
• pp.3-6
• /
• 2012

최근 응용 특화된 다양한 구조의 프로세서가 확산됨에 따라 기존 운영체제를 다른 구조의 플랫폼으로 이식하는 비용이 증가하고 있다. 기존 운영체제에서는 소스 코드 수준에서 하드웨어 의존적인 부분을 HAL(hardware abstraction layer)로 구분하여 관리함으로써 이기종 플랫폼간의 이식성을 높이고자 하였다. 그러나 기존 HAL 구조는 대부분 하드웨어의 물리적인 구조만을 고려하여 설계되어 체계적인 이식 작업이 어렵다는 문제점을 가지고 있다. 이를 위해 본 논문에서는 하드웨어의 물리적인 구조와 운영체제의 기능적인 요소를 함께 고려한 HAL 구조를 제안한다. 제안하는 HAL 구조의 효용성은 S3C2410 에서 실행하는 운영체제를 Cell BE 플랫폼으로 이식하는 사례 연구를 통해 검증하였다.

• Smart Media Journal
• /
• v.3 no.1
• /
• pp.33-38
• /
• 2014

Even though the performance of microprocessor is improved continuously, the performance improvement of computing system becomes hard to increase, in order to some drawbacks including increased power consumption. To solve the problem, general-purpose computing on graphics processing units(GPGPUs), which execute general-purpose applications by using specialized parallel-processing device representing graphics processing units(GPUs), have been focused. However, the characteristics of applications related with graphics is substantially different from the characteristics of general-purpose applications. Therefore, GPUs cannot exploit the outstanding computational resources sufficiently due to various constraints, when they execute general-purpose applications. When designing GPUs for GPGPU, memory system is important to effectively exploit the GPUs since typically general-purpose applications requires more memory accesses than graphics applications. Especially, external memory access requiring long latency impose a big overhead on the performance of GPUs. Therefore, the GPU performance must be improved if hierarchical memory architecture which can reduce the number of external memory access is applied. For this reason, we will investigate the analysis of GPU performance according to hierarchical cache architectures in executing various benchmarks.