• Title/Summary/Keyword: 유한버퍼

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Analytical Models and their Performance Analysis of Superscalar Processors (수퍼스칼라 프로세서의 해석적 모델 및 성능 분석)

  • Kim, Hak-Jun;Kim, Seon-Mo;Choe, Sang-Bang
    • Journal of KIISE:Computer Systems and Theory
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    • v.26 no.7
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    • pp.847-862
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    • 1999
  • 본 논문에서는 유한버퍼의(finite-buffered) 동기화된(synchronous) 큐잉모델(queueing model)을 이용하여 명령어들간의 병렬성, 분기명령의 빈도수, 분기예측(branch prediction)의 정확도, 캐쉬미스 등의 파라미터들을 고려하여 프로세서의 명령어 실행율을 예측하며 캐쉬의 성능과 파이프라인 성능간의 관계를 분석할 수 있는 새로운 해석적 모델을 제안하였다. 해석적 모델은 모델의 타당성을 검증하기 위해서 시뮬레이션을 수행하여 얻은 결과와 비교하였다. 해석적 모델과 시뮬레이션을 비교한 결과 대부분 10% 오차 내에서 일치하였다. 본 연구를 통하여 얻은 해석적 모델을 사용하면 시뮬레이션에서는 드러나지 않는 성능제약의 원인에 대한 명확한 규명이 가능하기 때문에 성능향상을 위한 설계자료를 얻을 수 있으며, 시스템 성능 밸런스를 위한 캐쉬와 비순차이슈 파이프라인 성능간의 관계에 대한 정확한 분석이 가능하다.Abstract This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc.. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error compared to simulation results. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.

Analysis of Heat Transfer around the High Level Waste Canisters (고준위 폐기물 처분용기 주변에서의 열전달 해석)

  • 최희주;최종원;이종열;권영주
    • Proceedings of the Korean Radioactive Waste Society Conference
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    • 2003.11a
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    • pp.270-275
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    • 2003
  • The heat transfer analysis was conducted for the conceptual design of high level waste canisters. The temperature distribution due to the heat generation from four PWR spent fuel bundles which were contained in a canister located in a borehole 500 m below the surface was obtained. NISA computer program based upon FEM was used for the numerical solution. The temperature distribution in the composite system of $\ulcorner$canister + buffer + tunnel + rock$\lrcorner$ due to heat generation from the spent fuel was obtained. In the case of 40m tunnel spacing and 6m borehole spacing the temperature showed the maximum value of $87.5^{\circ}C$around 15-16 years after disposal and decreased.

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A Segment Space Recycling Scheme for Optimizing Write Performance of LFS (LFS의 쓰기 성능 최적화를 위한 세그먼트 공간 재활용 기법)

  • Oh, Yong-Seok;Kim, Eun-Sam;Choi, Jong-Moo;Lee, Dong-Hee;Noh, Sam-H.
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.12
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    • pp.963-967
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    • 2009
  • The Log-structured File System (LFS) collects all modified data into a memory buffer and writes them sequentially to a segment on disk. Therefore, it has the potential to utilize the maximum bandwidth of storage devices where sequential writes are much faster than random writes. However, as disk space is finite, LFS has to conduct cleaning to produce free segments. This cleaning operation is the main reason LFS performance deteriorates when file system utilization is high. To overcome painful cleaning and reduced performance of LFS, we propose the segment space recycling (SSR) scheme that directly writes modified data to invalid areas of the segments and describe the classification method of data and segment to consider locality of reference for optimizing SSR scheme. We implement U-LFS, which employs our segment space recycling scheme in LFS, and experimental results show that SSR scheme increases performance of WOLF by up to 1.9 times in HDD and 1.6 times in SSD when file system utilization is high.

3D Display Method for Moving Viewers (움직이는 관찰자용 3차원 디스플레이 방법)

  • Heo, Gyeong-Mu;Kim, Myeong-Sin
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.37 no.4
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    • pp.37-45
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    • 2000
  • In this paper we suggest a method of detecting the two eyes position of moving viewer by using images obtained through a color CCD camera, and also a method of rendering view-dependent 3D image which consists of depth estimation, image-based 3D object modeling and stereoscopic display process. Through the experiment of applying the suggested methods, we could find the accurate two-eyes position with the success rate of 97.5% within the processing time of 0.39 second using personal computer, and display the view-dependent 3D image using Fl6 flight model. And through the similarity measurement of stereo image rendered at z-buffer by Open Inventor and captured by stereo camera using robot, we could find that view-dependent 3D picture obtained by our proposed method is optimal to viewer.

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FPGA Implementation for Real Time Sobel Edge Detector Block Using 3-Line Buffers (3-Line 버퍼를 사용한 실시간 Sobel 윤곽선 추출 블록 FPGA 구현)

  • Park, Chan-Su;Kim, Hi-Seok
    • Journal of IKEEE
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    • v.19 no.1
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    • pp.10-17
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    • 2015
  • In this Paper, an efficient method of FPGA based design and implementation of Sobel Edge detector block using 3-Line buffers is presented. The FPGA provides the proper and sufficient hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipe-lined method is used to implement the edge detector. The proposed Sobel edge detection operator is an model using of Finite State Machine(FSM) which executes a matrix mask operation to determine the level of edge intensity through different of pixels on an image. This approach is useful to improve the system performance by taking advantage of efficient look up tables, flip-flop resources on target device. The proposed Sobel detector using 3-line buffers is synthesized with Xilinx ISE 14.2 and implemented on Virtex II xc2vp-30-7-FF896 FPGA device. Using matlab, we show better PSNR performance of proposed design in terms of 3-Line buffers utilization.

양자우물 안에 양자점을 형성한 나노복합체 구조에 삽입된 InAs 양자점의 변형효과와 전자적 성질

  • Yu, Chan-Ho;Kim, Tae-Hwan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.308.1-308.1
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    • 2014
  • 반도체에서 양자점이 포함된 나노복합체의 전자적 구조와 성질에 대한 연구는 기본적인 양자 물리적 현상을 이해하고 전자소자 및 광소자의 다양한 응용 분야를 파생할 수 있기 때문에 많은 관심을 갖고 있다. 나노복합체를 구성하는 각각의 양자우물과 양자점에 대한 실험과 이론에 대한 연구는 많이 진행되고 있으며, 양자우물 안에 양자점이 삽입된 나노복합체에 대한 연구는 상대적으로 미흡한 상태이다. 또한 양자우물 안에 자발 형성된 양자점이 삽입된 나노복합체에 대한 전기적 특성 및 광학적 특성에 대한 연구는 많으나, 양자우물 안에 삽입된 양자점에 대한 전자적 구조에 대한 연구는 거의 없다. 양자우물 안에 양자점을 형성한 나노복합체 구조를 사용하여 제작한 전자소자와 광소자의 효율을 향상시키기 위해서는 이 복합 구조의 전자적 성질에 대한 연구가 필요하다. 본 연구에서는 단일 양자우물 안에 자발 형성된 InAs 양자점을 포함한 나노복합체의 전자적 특성을 분석하기 위하여 변형효과와 비포물선효과를 포함한 전자적 부띠 에너지에 대하여 비교 분석하였다. InAs 양자점은 20 nm의 직경을 갖고 있으며, GaAs 기판위에 버퍼층과 AlAs 층을 사용한 양자우물 구조에 삽입되었다. 단일 양자우물 안에 삽입된 양자점의 전자적 구조는 형상 의존 변형효과와 비포물선 효과를 고려한 쉬뢰딩거 방정식을 삼차원 가변 메시 유한차분법을 사용하여 수치해석 방법으로 분석하였다. 수치해석 방법으로 양자우물의 우물 폭의 영향을 받는 양자점의 크기변화에 따라 삼차원적인 전자 및 정공의 부띠 에너지와 기저상태 및 여기 상태의 파동 함수를 계산하였다. 이러한 결과는 나노복합체 안에 형성된 InAs 양자점의 전자적 특성을 이해하는데 도움을 주며, InAs가 포함된 나노복합체를 사용한 전자 소자와 광소자 연구에 기초 자료로 사용될 수 있다.

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Optimization of FPGA-based DDR Memory Interface for better Compatibility and Speed (호환성 및 속도 향상을 위한 FPGA 기반 DDR 메모리 인터페이스의 최적화)

  • Kim, Dae-Woon;Kang, Bong-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.12
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    • pp.1914-1919
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    • 2021
  • With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.