• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.43-51
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• 2012

This paper presents the design optimization technique for a phase interpolator(PI) and suggests the inductor-loaded PI structure for low power consumption suitable for high-speed applications. An analytical study leads to the design criterion composed of the process constants for the minimum power consumption and the proposed inductor-loaded PI reduces the power by half with determined bandwidth and gain of PI. Designed 7-bit PI using $0.13{\mu}m$ 1.2V CMOS technology consumes $721.2{\mu}W$ in 12GHz with inductor and the suggested optimization technique.