• Proceedings of the KIEE Conference
• /
• 2007.04a
• /
• pp.267-269
• /
• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.5
• /
• pp.77-86
• /
• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.4 s.119
• /
• pp.423-429
• /
• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.11 no.2
• /
• pp.179-184
• /
• 2016

The electrical load testing system developed from this study was designed to control rated-capacity-testing or variable-load-testing in an active and precise manner and save electric energy during testing, and also to convert the saved electric energy through the electrical load testing system to grid line. As for the device under testing, it was designed to be applied to not only transformer, rectifier, voltage regulator, inverter which require grid voltage source but, also applied to electric power, aerogenerator, photovoltaic, hybrid generator, battery, etc. which do not require grid voltage source. The system was designed to return the power consumed during the testing to the grid line by connecting the synchronizing pwm inverter circuit to the grid voltage source, and was also made to enable the being-tested system from disuse of approximately 93.4% energy when compared to the conventional load testing system which has used the passive resistor.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.38 no.4
• /
• pp.18-26
• /
• 2001

In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.6
• /
• pp.671-678
• /
• 2014

This paper presents a Ka-band FMCW sensor that has high linearity by improving a nonlinear behavior of the voltage controlled oscillator. Due to the nonlinear characteristics of the voltage controlled oscillator for the conventional method, the drift of beat frequency can cause inaccuracy and errors to the extracted results. A Ka-band FMCW signal with fast transition time could be generated by using both direct digital synthesizer and phase locked loop in this research. The implemented FMCW sensor showed very high accuracy in beat frequency through the test.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.7
• /
• pp.704-712
• /
• 2016

Recently, the installation of photovoltaic (PV) systems has been increasing due to the worldwide interest in eco-friendly and infinitely abundant solar energy. However, the output power of PV systems is highly influenced by the surrounding environment. For instance, a string of PV systems composed of modules in series may become inoperable under cloudy conditions or when in the shade of a building. In other words, under these conditions, the existing control method of PV systems does not allow the string to be operated in the normal way, because its output voltage is lower than the operating range of the grid connected inverter. In order to overcome this problem, we propose a new control method using a DC-DC voltage regulator which can compensate for the voltage of each string in the PV system. Also, based on the PSIM S/W, we model the DC-DC voltage regulator with constant voltage control & MPPT (Maximum Power Point Tracking) control functions and 3-Phase grid connected inverter with PLL (Phase-Locked Loop) control function. From the simulation results, it is confirmed that the present control method can improve the operating efficiency of PV systems by compensating for the fluctuation of the voltage of the strings caused by the surrounding conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.94-99
• /
• 2010

This paper presents a charge pump architecture for correcting the current mismatch due to the PVT variation. In general, the current mismatch of the charge pump should be minimized to improve the phase noise and spur performance of the PLL. In order to correct the current mismatch of the charge pump, the current difference is detected by the replica charge pump and fed back into the main charge pump. This scheme is very simple and guarantees the high accuracy compared with the prior works. Also, it shows a good dynamic performance because the mismatch is corrected continuously. It is implemented in 0.13um CMOS process and the die area is $100{\mu}m\;{\times}\;160{\mu}m$. The voltage swing is from 0.2V to 1V at supply voltage of 1.2V. The charging and discharging currents are $100{\mu}A$, respectively and the current mismatch due to the PVT variation is less than 1%.