• Title/Summary/Keyword: 웨이퍼 공정

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A Proposal of Sensor-based Time Series Classification Model using Explainable Convolutional Neural Network

  • Jang, Youngjun;Kim, Jiho;Lee, Hongchul
    • Journal of the Korea Society of Computer and Information
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    • v.27 no.5
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    • pp.55-67
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    • 2022
  • Sensor data can provide fault diagnosis for equipment. However, the cause analysis for fault results of equipment is not often provided. In this study, we propose an explainable convolutional neural network framework for the sensor-based time series classification model. We used sensor-based time series dataset, acquired from vehicles equipped with sensors, and the Wafer dataset, acquired from manufacturing process. Moreover, we used Cycle Signal dataset, acquired from real world mechanical equipment, and for Data augmentation methods, scaling and jittering were used to train our deep learning models. In addition, our proposed classification models are convolutional neural network based models, FCN, 1D-CNN, and ResNet, to compare evaluations for each model. Our experimental results show that the ResNet provides promising results in the context of time series classification with accuracy and F1 Score reaching 95%, improved by 3% compared to the previous study. Furthermore, we propose XAI methods, Class Activation Map and Layer Visualization, to interpret the experiment result. XAI methods can visualize the time series interval that shows important factors for sensor data classification.

Effect of oxidants and additives on the polishing performance in tungsten CMP slurry (텅스텐 CMP 연마액에서 산화제와 첨가제가 연마 성능에 미치는 영향)

  • Lee, Jae Seok;Choi, Beom Suk
    • Analytical Science and Technology
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    • v.19 no.5
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    • pp.394-399
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    • 2006
  • The polishing performance and the relationships of electrochemistry depending upon oxidizers and additives in the tungsten CMP slurry used in semiconductor industry were investigated. Hydrogen peroxide, ferric nitrate and potassium iodate were used as oxidizers and they showed different oxidation reactions on tungsten film depending on the kind of oxidizers and pH of slurry. The differences influenced the polishing performance. Etching reaction was predominated in the hydrogen peroxide. However, passivation reaction was prevailed in ferric nitrate and potassium iodate. TMAH and KOH raised the potential energy and removal rate of tungsten, and improved a dispersion characteristic of slurry by increasing absolute value of zeta potential. Addition of 100 ppm of poly(acrylic acid) of M.W. 250,000 improved dispersion ability.

Synthesis of PMMA/PU Composite Material Incorporating Carbon Nanotubes for Antistatic Semiconductor IC Tray with Excellent Electrical Conductivity (우수한 전기전도성을 함유한 탄소나노튜브를 포함하는 반도체 IC Tray 대전방지용 PMMA/PU 복합소재 합성)

  • Sangwook Park;Hayoon Lee;Changmin Lee;Jongwook Park
    • Applied Chemistry for Engineering
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    • v.35 no.3
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    • pp.260-265
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    • 2024
  • To synthesize an antistatic material for use in semiconductor wafer transport trays, in-situ polymerization of poly(methyl methacrylate) (PMMA) and polyurethane (PU) incorporating carbon nanotubes was designed and conducted. The newly synthesized composites were evaluated for their thermal and electrical conductivity properties under conditions mimicking commercial device manufacturing processes. Comparative analysis of their respective performances revealed that both PMMA and PU containing carbon nanotubes exhibited enhanced thermal properties and superior electrical conductivity as the nanotube content increased. Morphology of the composites synthesized via in-situ polymerization was confirmed to be excellent through FE-SEM analysis, demonstrating good dispersibility. Both PMMA and PU incorporating carbon nanotubes showed outstanding surface resistance values of 103 Ω/□, indicating their suitability as antistatic materials for semiconductor applications.

A Study on Analysis of electrolyzed water properties with pH changes (pH 변화에 따른 전리수 분석에 관한 연구)

  • Kim, Baekma;Kim, Minjung;Kim, Wohyuk;Kim, Bongsuk;Ryoo, Kunkul
    • Clean Technology
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    • v.10 no.1
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    • pp.47-51
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    • 2004
  • 현재 반도체 공정에서 사용되는 세정기술은 대부분이 1970년대 개발된 RCA 세정법인 과산화수소를 근간으로 하는 습식 세정으로, 표면의 입자를 제거하기 위한 SC-1 세정액은 강력한 산화제인 과산화수소에 의한 표면과 입자의 산화와 암모니아에 의한 표면의 에칭이 동시에 일어나 입자를 표면으로부터 분리시킨다. 금속 불순물을 제거하기 위한 SC-2 세정액은 염산과 과산화수소 혼합액을 사용하며 금속 불순물을 용해시켜 알칼리나 금속 이온을 형성하거나 용해 가능한 화합물을 형성시켜 제거한다. 또한 황산과 과산화수소를 혼합한 Piranha 세정액은 효과적인 유기물 제거제로서 웨이퍼에 오염된 유기물을 용해 가능한 화합물로 만들거나 과산화수소에 의해 형성되는 산화막내에 오염물을 포함시켜 불산 용액으로 산화막을 제거할 때 함께 제거된다. 최근 금속과 산화막을 동시에 제거하기 위해 희석시킨 불산에 과산화수소를 첨가한 세정공정이 사용되고 있으며 불산에 의해 표면의 산화막이 제거될 때 산화막내에 포함된 금속 불순물을 동시에 제거시킬 수 있다. 그러나 이와 같이 습식세정액 내에 공통적으로 포함되어 있는 과산화수소의 분해는 그만큼 가속화되어 사용되는 화학 약품의 양이 그만큼 증가하게 되고 조작하기 어려운 단점도 있다. 이를 해결하기 위해 환경친화적인 관점으로 화학약품의 사용을 최소화하는 등 RCA세정을 보완하는 연구가 계속 진행되고 있다. 본 연구에서는 RCA세정법을 환경적으로 대체할 수 있는 세정에 사용되는 전리수의 pH변화에 따른 전리수 분석을 하였다. 전리수의 제조를 위하여 전해질로는 NH4CI (HCI:H2O:NH4OH=1:1:1)를 사용하였다. pH 11 이상, ORP -700mV~-850mV인 환원수와 pH 3 이하, ORP 1000mV~1200mV인 산화수를 제조하였으며, 초순수를 첨가하여 pH 7.2와 ORP 351.1mV상태까지 조절하였다. 이렇게 만들어진 산화수와 환원수를 시간 변화와 pH 변화에 따라 Clean Room 안에서 FT-IR과 접촉각 측정기로 실험하였다. FT-IR분석에서 산화수는 pH가 높아질수록, 환원수는 낮아질수록 흡수율이 낮아졌다. 접촉각 실험에서는 산화수의 pH가 높아질수록 환원수의 pH가 낮아질수록 접촉각이 커짐을 확인하였다. 결론적으로 전리수를 이용하여 세정을 하면, 접촉성을 조절할 수 있어 반도체 세정을 가능하게 할 수 있으며, 환경친화적인 결과를 도출할 것으로 전망된다.

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Optimal Design of VCO Using Spiral Inductor (나선형 인덕터를 이용한 VCO 최적설계)

  • Kim, Yeong-Seok;Park, Jong-Uk;Kim, Chi-Won;Bae, Gi-Seong;Kim, Nam-Su
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.8-15
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    • 2002
  • We optimally designed the VCO(voltage-controlled oscillator) with spiral inductor using the MOSIS HP 0.5${\mu}{\textrm}{m}$ CMOS process. With the developed SPICE model of spiral inductor, the quality factor of spiral inductor was maximized at the operating frequency by varying the layout parameters, e.g., metal width, number of turns, radius, space of the metal lines. For the operation frequency of 2㎓, the inductance of about 3nH, and the MOSIS HP 0.5 CMOS process with the metal thickness of 0.8${\mu}{\textrm}{m}$, oxide thickness of 3${\mu}{\textrm}{m}$, the optimal width of metal lines is about 20${\mu}{\textrm}{m}$ for the maximum Quality factor. With the optimized spiral inductor, the VCO with LC tuning tank was designed, fabricated and measured. The measurements were peformed on-wafer using the HP8593E spectrum analyzer. The oscillation frequency was about 1.610Hz, the frequency variation of 250MHz(15%) with control voltage of 0V - 2V, and the phase noise of -108.4㏈c(@600KHz) from output spectrum.

대면적 Transformer coupled Plasma Source에서 파워결합에 관한 실험적 연구

  • 김희준;손명근;황용석
    • Proceedings of the Korean Vacuum Society Conference
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    • 1998.02a
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    • pp.166-166
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    • 1998
  • 반도체 공정에서 기존보다 큰 30cm 웨이퍼훌 이용하기 위해서 기존의 ECR, Helicon, ICP, 등 공정용 고 밀도 플라즈마 원들의 대면적화에 대한 연구가 세계적으로 진행되고 있다 현 상황에서는 평판형 안테 나룰 이용한 TCP가 대면적용 폴라즈마 원의 가장 유력한 후보로 여겨지고 있다 TCP롤 대면적화 하는 데 있어서 중요한 문제점으로는 대면적에서의 큰 안테나 인되턴스로 인한 임피던스 정합과 대면적에서 의 유전울질의 기계적 강도이다. 앓은 유전물질올 사용힐 수 있도록 대면적 TCP 플라즈마 원올 실계 저l작하였고 이차원 가열이론올 이용한 TCPRP code 률 이용하여 안테나의 반경옳 결정하였디 안테나의 인덕턴스 값올 줄이기 위해서는 주m수는 13.56MHz 보다 낮은 4-5MHz 부근에서 작동하는 RF 파워룰 선택하였다 이 파워 서플라이는 보통 사용되는 50n 흩력 입묘$\mid$던스훌 갖는 형태가 Of니라 LC 공진현상 올 이용하여 부하에 파워률 전달하는 형태이다 .. TCP 장치에 사용할 수 있도록 파워 서플라이 흩력 단에 안테나와 직혈로 가변 콘덴서를 달아서 임11I던스 정합올 힐 수 있게 하였다 안테나에 직훌로 달Of줌으 로써 안테니의 인덕턴스훌 훌여주는 효과훌 얻올 수 있다 안테나에 흐르는 전류룰 측정하기 위해서 사 각형 루프로 전류 픽업 코일을 만들었고 진공상태에서 RF 파워률 인가하고 안테나의 전류와 전압을 측정하여 픽업 코일걸과훌 조정하였다. 발생기체로는 헬륨올 사용하였고 1-100mTorr 의 압력범위에서 실험을 하였다 플라즈마롤 빌샘시키고 파워를 증가 시킴에 따라 E-H mode transition 현상이 관찰되었고 그 때의 임계 전류 값을 측정하였다. 압력이 낮올수록 모드 변화가 일어나는 전류의 값이 작았다 임계 전류는 압력에 대해서 선형적인 특성을 보였다 이는 압력이 낮을수록 유도걸힘이 더 잘 된다는 것을 의미한다 1 1 mTorr에서는 H-mode에서 안테나의 전류가 파워훌 증가시킴에 따라 계속 증가하였으니, 압력이 올라 갈수록 조금씩 증가하는 정도가 줄어들고. 100mTorr에서는 포화된 값을 나타냈다 H-mode로 넘어간 후 에는 파워가 증가황에 따라 안테나의 임피던스 값이 모든 압력영역에서 줄어드는 경황을 보였고, 이는 플라즈마의 인덕턴스에 의해서 안테나의 인덕턴스 기 감소되기 때문이다, 파워가 증가할수록 안테U오} 플라즈마 루프사이의 상호걸합이 증가하는 걸로 해석힐 수 있다 안테나의 인되턴스 변화보다는 저항.성 분의 변화가 컸다 하지만 전체 임피던스로 볼 때 저항성분이 상대적으로 작기 때문에 인덕턴스의 감소 가 더 큰 영향을 미치는 걸로 볼 수 있다. 하지만 플라즈마로의 파워 전달에는 저항성분만이 영향올 미 치므로 저항성분의 큰 변화는 파워가 많이 전달될올 의미한다 피워전달 효율을 계산해 본 결과 수 r mTorr 부근이 80-90% 정도의 높은 효율올 보였고 5mTorr 일 때가 가장 좋았다.

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Design of a Large-density MTP IP (대용량 MTP IP 설계)

  • Kim, YoungHee;Ha, Yoon-Kyu;Jin, Hongzhou;Kim, SuJin;Kim, SeungGuk;Jung, InChul;Ha, PanBong;Park, Seungyeop
    • Journal of IKEEE
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    • v.24 no.1
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    • pp.161-169
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    • 2020
  • In order to reduce the manufacturing cost of MCU chips used in applications such as wireless chargers and USB-C, compared to DP-EEPROM (Double Poly EEPROM), which requires 3 to 5 additional process masks, it is even more necessary MTP(Multi-Time Programmable), which is less than one additional mask and have smaller unit cell size. In addition, in order to improve endurance characteristics and data retention characteristics of the MTP memory cell due to E/P(Erase / Program) cycling, the distribution of the VTP(Program Threshold Voltage) and the VTE(Erase Threshold Voltage) needs to be narrow. In this paper, we proposed a current-type BL S/A(Bit-Line Sense Amplifier) circuit, WM(Write Mask) circuit, BLD(BL Driver) circuit and a algorithm, which can reduce the distribution of program and VT and erase VT, through compare the target current by performing the erase and program pulse of the short pulse several times, and if the current specification is satisfied, the program or erase operation is no longer performed. It was confirmed that the 256Kb MTP memory fabricated in the Magnachip semiconductor 0.13㎛ process operates well on the wafer in accordance with the operation mode.

Polymer-based Large Core Optical Splitter for Multimode Optical Networks (멀티모드 광네트워크용 폴리머기반 대구경 광분배기)

  • An, Jong Bae;Lee, Woo-Jin;Hwang, Sung Hwan;Kim, Gye Won;Kim, Myoung Jin;Jung, Eun Joo;Moon, Jong Ha;Kim, Jin Hyeok;Rho, Byung Sup
    • Korean Journal of Optics and Photonics
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    • v.24 no.4
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    • pp.184-188
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    • 2013
  • Two types of polymer-based optical splitters with $200{\mu}m$ large core are presented for optical multimode networks, such as smart home networks, intelligent automotive networks, etc. Optical splitters that have 1:1 symmetric and 9:1 asymmetric structure were fabricated by a ultra violet(UV)-imprint technology using a deep etched Si(silicon) master by the Bosch process. In this paper, we successfully fabricated the symmetric and asymmetric optical splitters with suitable optical network applications.

Design of Synchronous 256-bit OTP Memory (동기식 256-bit OTP 메모리 설계)

  • Li, Long-Zhen;Kim, Tae-Hoon;Shim, Oe-Yong;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.7
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    • pp.1227-1234
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    • 2008
  • In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

Synthesis of Pressure-sensitive Acrylic Adhesives with Photoreactive Groups and Their Application to Semiconductor Dicing Tapes (광 반응성기를 갖는 아크릴 점착제의 합성과 반도체 다이싱 테이프로의 적용 연구)

  • Hee-Woong Park;Nam-Gyu Jang;Kiok Kwon;Seunghan Shin
    • Applied Chemistry for Engineering
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    • v.34 no.5
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    • pp.522-528
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    • 2023
  • In this work, adhesive tapes were prepared for the dicing process in semiconductor manufacturing. Compounds with different numbers of photoreactive groups (f = 1 to 3) were synthesized and incorporated into acrylic copolymers to formulate UV-curable acrylic adhesives. Structural confirmation of the synthesized photoreactive compounds (f = 2 or 3) was performed using nuclear magnetic resonance (NMR) spectroscopy. The introduction of the photoreactive compounds into the acrylic adhesive was accomplished by urethane reactions, and the successful synthesis of the UV-curable acrylic adhesive was verified by Fourier transform infrared (FT-IR) measurements. To evaluate the performance of the adhesive, the peel strength was evaluated before and after UV irradiation using a silicon wafer as a substrate. The adhesive exhibited high peel strength (~2000 gf/25 mm) before UV exposure, which was significantly reduced (~5 gf/25 mm) after UV exposure. Interestingly, the adhesive containing multifunctional photoreactive compounds showed the most significant reduction in peel strength. In addition, surface residue measurements by field emission scanning electron microscopy (FE-SEM) showed minimal surface residue (~0.2%) after UV exposure. Overall, these results contribute to the understanding of the behavior of UV-curable acrylic adhesives and pave the way for potential applications in semiconductor manufacturing processes.