• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2315-2318
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• 2003

The Wavelet Transform has been applied in mathematics and computer sciences. Numerous studies have proven its advantages in image processing and data compression, and have made it a basic encoding technique in data compression standards like JPEG2000 and MPEG-4. Software implementations of the Discrete Wavelet Transform (DWT) appears to be the performance bottleneck in real-time systems in terms of performance. And hardware implementations are not flexible. Therefore, FPGA implementations of the DWT has been a topic of recent research. The goal of this thesis is to investigate of FPGA implementations of the DWT Processor for image compression applications. The DWT processor design is based on the Lifting Based Wavelet Transform Scheme, which is a fast implementation of the DWT The design uses various techniques. The DWT Processor was simulated and implemented in a FLEX FPGA platform of Altera

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3224-3226
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• 1999

This paper introduces a nonlinear wavelet transform based on the lifting scheme, which is applied to signal denoising through the translation invariant wavelet transform. The wavelet representation using orthogonal wavelet bases has received widespread attention. Recently the lifting scheme has been developed for the construction of biorthogonal wavelets in the spatial domain. In this paper, we adaptively reduce the vanishing moments in the discontinuities to suppress the ringing artifacts and this customizes wavelet transforms providing an efficient framework for the translation invariant denoising. Special care has been given to the boundaries, where we design a set of different prediction coefficients to reduce the prediction error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.993-1000
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• 2012

In this research, we proposed an efficient VLSI architecture of the lifting-based 2D DWT (Discrete Wavelet Transform) filter with 100% hardware utilization. The (9,7) filter structure has been applied and extendable to the filter length. We proposed a new block-based scheduling that computes the DWT for the lower levels on an "as-early-as-possible" basis, which means that the calculation for the lower level will start as soon as the data is ready. Since the proposed 2D DWT computes the outputs of all levels by one row-based scan, the intermediate results for other resolution levels should be kept in storage such as the Data Format Converter (DFC) and the Delay Control Unit (DCU) until they are used. When the size of input image is $N{\times}N$ and m is the filter length, the required storage for the proposed architecture is about 2mN. Since the proposed architecture processes the 2D DWT in horizontal and vertical directions at the same time with 4 input data, the total period for 2D DWT is $N^2(1-2^{-2J})/3$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.785-792
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• 2004

In this paper, we propose a fast and efficient method that improves the performance of embedded zerotree wavelet(EZW) algorithm introduced by Sharipo． In the EZW algorithm, two bits are allocated for a symbol, but it is inefficient for compression and the zerotree coding wastes much time at encoding. In this paper, in order to increase the efficiency of compression, it will be allocated a variable bit for a symbol at each subband. To reduce the encoding time, we use a backscan method and lifting scheme instead of filter bank in wavelet transform. Experimental result are shown that the algorithm suggested in this paper has a better performance about 0.3∼1.5㏈ PSNR while the encoding time was speeded up more than 2-10 times compared with the EZW algorithm.

• Journal of Broadcast Engineering
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• v.12 no.2
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• pp.185-192
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• 2007

The interpolation is used in many image processing applications such as image enhancement, de-interlacing/scan-rate conversion, wavelet transforms based on the lifting scheme, and so on. Among these, de-interlacing and scan-rate conversion are proposed for the digital TV applications. The de-interlacing algorithm can be classified into two categories. The first one uses only one field, called intra-field de-interlacing, and the other uses multiple field, called inter-field de-interlacing. In this paper, an efficient de-interlacing algorithm using spatial domain information is proposed far the interpolation of interlaced images. By efficiently estimating the directional correlations, improved interpolation accuracy has been achieved. In addition, the proposed method is simply structured and is easy to implement. Extensive simulations conducted for various images and video sequences have shown the efficacy of the proposed method with significant improvement over the previous intra-field do-interlacing methods in terms of the objective image quality as well as the subjective image quality.

• Journal of Korea Multimedia Society
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• v.10 no.10
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• pp.1271-1283
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• 2007

To detect defect of FPD(flat panel displays) is very difficult due to uneven illumination on FPD panel image. This paper presents a method to detect various types of defects using the approximated image of the uneven illumination by B-spline. To construct a approximated surface, corresponding to uneven illumination background intensity, while reducing random noises and small defect signal, only the lowest smooth subband is used by wavelet decomposition, resulting in reducing the computation time of taking B-spline approximation and enhancing detection accuracy. The approximated image in lowest LL subband is expanded as the same size as original one by wavelet reconstruction, and the difference between original image and reconstructed one becomes a flat image of compensating the uneven illumination background. A simple binary thresholding is then used to separate the defective regions from the subtracted image. Finally, blob analysis as post-processing is carried out to get rid of false defects. For applying in-line system, the wavelet transform by lifting based fast algorithm is implemented to deal with a huge size data such as film and the processing time is highly reduced.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.42-50
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• 2008

The real-time bio-signal monitoring system based on the ZigBee and SIP/RTP has proposed and implemented for telemedicine but that has some problems at the stabilities to transmit bio-signal from the sensors to the other sides. In this paper, we designed and implemented a real-time bio-signal monitoring system that is focused on the reliability and efficiency for transmitting bio-signal at real-time. We designed the system to have enhanced architecture and performance in the ubiquitous sensor network, SIP/RTP real-time transmission and management of the database. The Bluetooth network is combined with ZigBee network to distribute traffic of the ECG and the other bio-signal. The modified and multiplied RTP session is used to ensure real-time transmission of ECG, other bio-signals and speech information on the internet. The modified ECG compression method based on DWLT and MSVQ is used to reduce data rate for storing ECG to the database. Finally we implemented a system that has improved performance for transmitting bio-signal from the sensors to the monitoring console and database. This implemented system makes possible to make various applications to serve U-health care services.