• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.122-128
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• 2002

푸리에 변환을 사용하는 제1세대 웨이블릿은 정규화된 그리드에서만 적용되는 반면 리프팅 스킴을 사용한 제2세대 웨이블릿은 불규칙한 그리드를 처리할 수 있다. 본 논문에서는 제2세대 웨이블릿 생성 도구인 리프팅 스킴을 사용하여 압축된 적은 데이터를 사용한 근사치 영상을 생성하는 방법으로 부분 복원과 공간 복원 알고리즘과 리프팅 스킴을 이용한 에지 검출 기법이 제안되었다.

• Journal of Korea Multimedia Society
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• v.6 no.5
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• pp.805-815
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• 2003

In this paper, we present the development of document compression codec using segmentation, wavelet lifting and bitplane coding. We use the segmentation to preserve the text appearance. We performed integer-to-integer wavelet lifting and also performed bitplane subblock coding for document compression. We acquired a high compression ratio and an efficient compression by encoding only the significant subblocks in the bitplane subblock coding. We also implemented scalar quantization by subband-oriented bit shifting. The system performs color conversion and downsampling before wavelet lifting and also performs graycode conversion and quantization before subblock coding. In the experiment, we show the performances of the system by presenting the high compression ratios and high PSNR values.

• Journal of Korea Multimedia Society
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• v.8 no.1
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• pp.19-26
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• 2005

The basis function of wavelet transform used in this paper is constructed by using lifting scheme, which is different from general wavelet transform. Lifting scheme is a new biorthogonal wavelet con-structing method, that does not use Fourier transform for constructing its basis function. In this paper, an image compression and reconstruction method using the lifting scheme was proposed. And this method improves data visualization by supporting a partial reconstruction and a local reconstruction. Approx- imations at various resolutions allow extracting various sizes of feature from an image or signal with a small amount of original information. An approximation with small size of scaling coefficients gives a brief outline of features at fast. Image compression and edge detection techniques provide good frame- works for data management and visualization in multimedia database.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1409-1418
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• 2001

영상 압축 분야에서 많은 정수 웨이블릿 변환들이 손실 압축 성능, 무 손실 압축 성능, 그리고 복잡성을 기준으로 비교되었다. 응용분야에 따라서 상대적인 조건에 의한 최적인 웨이블릿 변환을 선택함에 따라서 여러 웨이블릿 변환들 중에서 상대적으로 우수한 변환들이 존재함이 알려졌다. 본 논문에서는 우수한 성능을 보이는 웨이블릿 필터들을 리프팅 기법을 응용해서 통합한다. 이들 우수한 몇 개의 변환들은 간단한 파라미터로 표현이 가능하고 이들 파라미터들은 주어진 입력 영상에 종속적이다. 본 논문에서는 이들 파라이터를 구현하는 이론적인 결과와 실험결과를 제공한다. 제안된 방법이 S+P[2] 방법보다 대다수 경우에서 우수함을 실험결과로서 보여주고 있다.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.374-387
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• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.409-412
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• 2003

In this paper, the encoder architecture of 3-D wavelet transform based on lifting scheme is designed. Architecture, here, 3 level wavelet transform for spatial decomposition and 2 level wavelet transform for temporal decomposition is adopted with efficient computation.

• Journal of KIISE:Software and Applications
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• v.30 no.7_8
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• pp.687-695
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• 2003

In this paper, we present a document image compression system based on segmentation, Quincunx downsampling, (5/3) wavelet lifting and subband-oriented SPIHT coding. We reduced the coding time by the adaptation of subband-oriented SPIHT coding and Quincunx downsampling. And to increase compression rate further, we applied arithmetic coding to the bitstream of SPIHT coding output. Finally, we present the reconstructed images for visual comparison and also present the compression rates and PSNR values under various scalar quantization methods.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.113-116
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• 2001

제로트리 부호화 알고리즘 중 효율적이며 잘 알려진 SPIHT는 높은 메모리 요구로 인해 하드웨어 구현에 큰 어려움을 가지고 있다. 이 논문에서는 저 메모리 사용과 빠른 제로트리 부호화 알고리즘을 제안한다. 메모리를 줄이고 빠른 코딩을 위한 방법으로 다음 3가지를 사용한다. 첫 번째, 리프팅을 이용한 웨이블릿 변환은 기존의 필터뱅크 방식의 변환보다 저 메모리와 계산량의 감소를 가진다. 두 번째, 웨이블릿 변환된 계수들은 블럭으로 나누어져 각각 코딩된다. 여기서 블록은 제로트리 구조가 유지되는 STB(spatial tree-based block)이다. 세 번째, Wheeler 와 Pearlman이 제안한 NLS (no list SPIHT)를 이용한 부호화이다. NLS는 효율성에서 SPIHT와 거의 같으며 작고 고정된 메모리와 빠른 부호화 속도를 보여준다.