• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.421-430
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• 2003

In the embedded system, EPROM is difficult to replace a mask ROM for the applications using battery, because the low voltage characteristic of an EPROM is inferior to that of a mask ROM. In this paper, the new circuits such as a word line voltage hoosier scheme and a sense amplifier without reference input for an embedded EPROM in MCU are proposed. The circuits can detect bit line voltage a predetermined level, which is caused by the degradation of the battery. We fabricated a MCU embedded 32Kbytes EPROM. The proposed circuits well operated at 1.5V supply voltage and thus the low voltage performance was improved by about 30%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.28-35
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• 2007

In this paper, an ultra low voltage SRAM design method based on dual-boosted cell bias technique is described. For each read/write cycle, the wordline and cell power node of the selected SRAM cells are boosted into two different voltage levels. This enhances SNM(Static Noise Margin) to a sufficient amount without an increase of the cell size, even at sub 1-V supply voltage. It also improves the SRAM circuit speed owing to increase of the cell read-out current. The proposed design technique has been demonstrated through 0.8-V, 32K-byte SRAM macro design in a $0.18-{\mu}m$ CMOS technology. Compared to the conventional cell bias technique, the simulation confirms an 135 % enhancement of the cell SNM and a 31 % faster speed at 0.8-V supply voltage. This prototype chip shows an access time of 23 ns and a power dissipation of $125\;{\mu}W/Hz$.