• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.795-797
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• 2013

This paper describes a charge sharing capacitive-sensing circuit technique that improves the quality of images captured with fingerprint sensor LSIs. When the finger is dry, the electrical resistance of a finger surface is high. It leads to poor image quality. To capture clear images even when the finger is dry, the modified capacitive detection circuit improves the image quality using an enhancement plate at the finger surface and a voltage control circuit. The test circuit is analyzed on $0.35{\mu}m$ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1343-1348
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• 2011

A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than a conventional circuit. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process, 40MHz condition. The result shows about 47% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is layout without area increasing of a one pixel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.65-71
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• 2007

We propose a pixel-level automatic calibration circuit scheme that initializes a capacitive fingerprint sensor LSI to eliminate the influence of the surface condition and environment, which is degraded by dirt during long-time use, process variation and ambient temperature. The sample chip is fabricated on $0.35{\mu}m$ standard CMOS process. The calibration is executed by optimizing the reference voltage in each pixel to make the sensor signals of all pixels the same. The calibration control circuit is composed of the sensing circuit and charge pumping circuit, and calibrates all pixels in a short time. 16-level gray scale fingerprint images can be captured to increase the accuracy of identification. This confirms that the scheme is effective for capturing consistent clear images during long-time use.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.63-69
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• 2012

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.