• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.82-90
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• 2013

An Optical Network-on-Chip(ONoC) based on silicon photonics is one of promising technology for next generation exascale computing architectures. Recent active researches on ONoC focus on improving bandwidth further and avoiding path collisions by using wavelength division multiplexing (WDM). However, the number of wavelengths used for the WDM increases linearly as the number of Processing Element (PE) increases in existing ONoCs which adopt centralized routing architecture. The problem will also arises growing cost of optical devices such as light switches and light sources and limits the scalability of ONoC due to the sinal loss caused by interference of distinct light sources. In this paper, we proposes a distributed routing architecture for ONoC which is based on 2D-mesh structure using WDM technique and present a method that minimize the required number of wavelengths exploiting the connectivity of communication. In comparison with existing centralized routing architectures, results show reduction by 56% of the number of wavelengths and 21% of the number of optical switches in $8{\times}8$ networks.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.220-223
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• 2012

매니코어 시스템에서는 프로그램의 확장성에 대한 정보가 코어와 같은 병렬 자원의 할당 문제 해결에 핵심적인 역할을 한다. 본 논문에서는 Cilk 런타임 시스템에서 구동되는 응용 프로그램들에 대한 확장성 모델을 제안하여 매니코어 시스템에서의 효율적인 자원 관리에 활용하고자 한다. 특히, 네트워크- 온-칩 구조 및 디렉터리 기반 캐시 일관성 프로토콜을 감안한 지연 시간 모델링을 통해 보다 정확한 성능 변화의 경향을 예측하고자 하였다. 최대 36 개까지의 코어 할당에 대한 지연 시간 예측 실험에서, 제안된 모델은 13%의 평균 오차를 보였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.251-254
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• 2010

현대사회의 전자와 물리공간의 융합인 유비쿼터스가 진행되고 있다. 이 유비쿼터스 사회가 가능하려면 모든 사물에 컴퓨터 칩인 RFID태그가 부착되어야 한다. RFID는 무선을 통하여 사물의 ID정보를 제공하며, 향후 주변의 상황정보(온도, 습도, 오염정보, 균열정보 등)까지 탐지하여 이를 실시간으로 네트워크에 연결하여 정보를 관리하는 것이다. 앞으로 이 RFID가 가정에서 모든 기기에 부착되어. 시스템화가 된다면 유비쿼터스 가정이 된다. 본 논문에서는 유비쿼터스 사회의 기술적 정의와 자동화 된 지역내 환경제어를 위한 네트웍크를 구현하기 위한 RFID/USN에 대하여 연구하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.554-561
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• 2006

In recent years, as SoC design research is actively conducted, a large number of IPs are included in a system. Various bus protocols and bus architectures are designed to increase IP reusability. Among them, the AMBA AHB became a de facto standard although it is somewhat inadequate for a large scale SoC. We proposed SNP and SNA, high performance on-chip-bus protocol and architecture, respectively, to solve the problem of the conventional shared buses. However, it seems to be imperative that the new on-chip-bus system support AMBA-compatible IPs for a while since there are a lot of IPs with AMBA interface. In this paper, we propose an extended SNP specification and a corresponding SNA component to support ABMA-compatible IPs used in SNA - based system. We extend the phase of the SNP by 1 bit to add new 8 phases to support communication based on AMBA protocol without penalty of elongated cycle latency. The ARB-to -XSNP converter translates the protocol between AHB and SNP to attach AMBA -compatible IPs to SNA based system. We show that AMBA IPs can communicate through SNP without any degradation of performance using the extended SNP and AHB - to- XSNP converter.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.66-75
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• 2016

Due to aggressive scaling of device sizes and reduced noise margins, physical defects caused by aging and process variation are continuously increasing. Additionally, with scaling limitation of metal wire and the increasing of communication volume, fault tolerant method in manycore network-on-chip (NoC) has been actively researched. However, there are few researches investigating reliability in NoC with voltage-frequency-island (VFI) regime. In this paper, we propose a table-based routing technique that can communicate, even if link failures occur in the VFI NoC. The output port is alternatively selected between best and the detour routing path in order to improve reliability with minimized hardware cost. Experimental results show that the proposed method achieves full coverage within 1% faulty links. Compared to $d^2$-LBDR that also considers a routing method for searching a detour path in real time, the proposed method, on average, produces 0.8% savings in execution time and 15.9% savings in energy consumption.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.462-469
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• 2008

In this paper, we design the FPGA (Field-Programmable Gate Array) of the KOINONIA WPAN (Wireless Personal Area Network), and implement the SoC (System on Chip). We use the redundant bits to make a constant-amplitude in a modulator part. Additionally, the SNR (Signal to Noise Ratio) performance of the demodulator is improved by using the redundant bits in decoding steps. The four-million FPGA of the KOINONIA WPAN can be operated at 44MHz frequency. The PER (Packet Error Rate) of the designed FPGA with RF (Radio Frequency) module is below 1% at the -86dB MIPLS (Minimum Input Power Level Sensitivity), and the SNR is about 13dB. The SoC is implemented by using Hynix 0.25um CMOS (Complementary Metal Oxide Semiconductor) process. The size of the SoC is $6.52mm{\times}6.92mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.1-6
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• 2007

Wireless Self-Powered Temperature Sensor for UHF Sensor Tags which are basic device for construction of ubiquitous sensor network is proposed. The key parameters of the target specification are resolution of $0.1\;^{\circ}C$ per output bit, below 1.5 V of operating voltage and below 5 uW of power consumption during sensing operation. Temperature sensor circuit consists of PTAT current generator, band gap reference circuit generating both reference voltage and current, Sigma-Delta Converter, and Digital Counter. Simulated maximum resolution was $0.23\;^{\circ}C/bit$ in 11-bit output. The proposed temperature sensor was fabricated by using a 0.25 m CMOS process. The chip area is $0.32\;{\times}\;0.22\;mm$ and the operating frequency is 2 MHz. Measured resolution from fabricated temperature sensor was $4\;^{\circ}C/bit$ in 8-bit output for the temperature range from $10^{\circ}C$ to $80^{\circ}C$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.