• Journal of Aerospace System Engineering
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• v.18 no.4
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• pp.89-95
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• 2024

This paper introduces an effective and convenient method for utilizing onboard memory space to process remote commands, telemetry, and interplanetary network protocol data in satellite onboard systems. By enhancing the doubly linked list data structure to store and make accessible variable-length communication protocol data either sequentially or at variable locations, the paper enhances memory capacity utilization. The concept of 'grape' is introduced into the doubly linked list data structure to manage variable-length data and its access, with performance verification conducted through its reference implementation. This novel approach to linked lists is termed 'grape.'

• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.325-327
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• 2011

온보드 대상의 디버깅은 타깃머신의 처리 속도 및 통신 속도의 제약으로 인해 발생하는 지연시간 때문에 개발 기간이 길어지게 된다. 이런 문제를 해결하고자 소프트웨어 에뮬레이터를 상위 성능의 머신에서 구동하고 온보드로는 인스트럭션과 그에 필요한 데이터의 전송만 진행하여 온보드로부터의 메모리 전송을 최소화함으로써 지연시간을 감소시키는 효과를 얻을 수 있다. 본 논문에서는 Zaram사(社)의 CDSP16V2 프로세서를 위한 디버거 성능 개선 방법 및 구현에 대하여 서술한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.9
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• pp.991-998
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• 2014

Embedded System operates hardware installed like processor, memory device, various input/output devices and software to control them. This thesis presents MPU module and Base board which are efficient industrial control through design and manufacture as developing S5PV210 CPU of SAMSUNG used by ARM Cortex-A8 based on Android which is Open mobile platform is installed to embedded system. Data for temperature and humidity which are received by CAN communication module proved the suitability and validity for the embedded platform design as implementing application program employed the native App with Linux Kernel based on the Android OS and application of HTML5.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.245-252
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• 2003

We designed a silicon pressure sensor interface circuit with digital calibration capability. The interface circuit is composed of an analog section and a digital section. The analog section amplifies the weak signal from the sensor and the digital section handles the calibration function and communication function between the chip and outside microcontroller that controls the calibration. The digital section is composed of I2C serial interface, memory, trimming register and controller. The I2C serial interface is optimized to suit the need of on-chip silicon microsensor in terms of number of IO pins and silicon area. The major part of the design is to build a controller circuit that implements the optimized I2C protocol. The designed chip was fabricated through IDEC's MPW. We also made a test board and the test result showed that the chip performs the digital calibration function very well as expected.