• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.31-42
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• 2005

ATSC DTV system uses FPLL block for acquiring the frequency synchronization. Because the FPLL uses only the pilot signal, the frequency convergence range becomes narrower and it takes a more time to acquire the frequency synchronization as the pilot is distorted. And the spectrum shape around the pilot makes an asymmetric convergence range between the positive frequency offset and the negative frequency offset. This paper proposes the algorithm that requires the Installation of the fitters at the both edges of a VSB spectrum and uses the signal power that passes these filters. The proposed algorithm complements the problems of the asymmetric convergence range and overcomes the performance degradation due to the distortion of a pilot level.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.5
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• pp.27-33
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• 2011

In digital communication system that the Modified Constant Modulus Algorithm (MCMA) reduced the use of the adaptive equalization algorithm to combat the Inter-symbol Interference (ISI). MCMA is relatively brief operation. The major point of MCMA that it only achieves moderate convergence rate and steady state mean square error (MSE). In this paper suggest, MCMA equalization improve the performance with parallel structure. It combines Modified Constant Modulus Algorithm(MCMA) and Modified Decision Directed(MDD) algorithm. By exploiting the inherent structural relationship between the 4-QAM signal's coordinates and 16-QAM signal's coordinates, another style of cost function for Modified Constant Modulus Algorithm(MCMA) is defined and If it happen to offset of received signals and MCMA is poor performance in order to overcome this because the paper combines apply for MCMA and MDD(Modified Decision Direct) algorithm. By computer simulation, we confirmed that the proposed PMCMA-MDD algorithm has the fater convergence rate and steady mean square error than the conventional MCMA.

• Journal of Navigation and Port Research
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• v.26 no.2
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• pp.215-220
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• 2002

In this paper, the 100 watt unit ower amplifier using temperature independent biasing for DTV (Digital Television) repeater application is designed and fabricated. The DC operation point of this unit power amplifier at temperature variation from $20^{\circ}C$ to $100^{\circ}C$ is fixed by active bias circuit. The variation of current consumption in the 100 watt unit power amplifier has an excellent characteristics of less than 0.6A. The implemented unit power amplifier has the gain over 12dB, the gain flatness of less than 0.5dB and input and output return, loss of than 15dB over the DTV repeater frequency range (470~806MHz). This unit power amplifier yields intermodulation distortion(IMD) of more than 32dBc at 2MHz offset, which satisfies the IMD at output power of 100 watt (50dBm).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• The KIPS Transactions:PartD
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• v.19D no.2
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• pp.161-186
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• 2012

Recently, the flash memory consistently increases the storage capacity while the price of the memory is being cheap. This makes the mass storage SSD(Solid State Drive) popular. The flash memory, however, has a lot of defects. In order that these defects should be complimented, it is needed to use the FTL(Flash Translation Layer) as a special layer. To operate restrictions of the hardware efficiently, the FTL that is essential to work plays a role of transferring from the logical sector number of file systems to the physical sector number of the flash memory. Especially, the poor performance is attributed to Erase-Before-Write among the flash memory's restrictions, and even if there are lots of studies based on the log block, a few problems still exists in order for the mass storage flash memory to be operated. If the FAST based on Log Block-Based Flash often is generated in the wide locality causing the random writing, the merge operation will be occur as the sectors is not used in the data block. In other words, the block thrashing which is not effective occurs and then, the flash memory's performance get worse. If the log-block makes the overwriting caused, the log-block is executed like a cache and this technique contributes to developing the flash memory performance improvement. This study for the improvement of the random writing demonstrates that the log block is operated like not only the cache but also the entire flash memory so that the merge operation and the erase operation are diminished as there are a distinct mapping table called as the offset mapping table for the operation. The new FTL is to be defined as the XAST(extensively-Associative Sector Translation). The XAST manages the offset mapping table with efficiency based on the spatial locality and temporal locality.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.12
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• pp.1223-1231
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• 2010

The design is presented for a SATCOM antenna capable of simultaneous multi-band (X/Ku/Ka-Band) communications without replacement of feed horns or change of other parts in the application as a ground satellite terminal for large data transfer. The antenna is the offset configuration and consists of a dual-band(X/Ka-band) feed horn, a single-band(Ku-band) feed horn, a frequency selective surface(FSS) sub-reflector and a parabolic main-reflector. The antenna has a main reflector defining a prime focus and a frequency selective surface sub-reflector defining an image focus. A dual-band feed and a single-band feed are provided at each of the prime focus and image focus. The antenna is designed using 3D EM simulator and the gains measured in X/Ku/Ka-band of the complete antenna assembly is more than 31.6dBi, 36.8dBi, 40.8dBi, and the cross polarization is 21.7dB, 26.6dB, 25.2dB, respectively.