• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.4
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• pp.237-247
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• 2003

The Motion Estimation (ME) process is an important part of a video encoding systems since they can significantly reduce bitrate with keeping the output quality of an encoded sequence. Unfortunately this process may dominate the encoding time using straightforward full search algorithm (FS). Up to now, many fast algorithms can reduce the computation complexity by limiting the number of searching locations. This is accomplished at the expense of less accuracy of motion estimation. In this paper, we introduce a new fast motion estimation method based on the spatio-temporal correlation of adjacent blocks. A reliable predicted motion vector (RPMV) is defined. The reliability of RPMV is shown on the basis of motion vectors achieved by FS. The scalar and the direction of RPMV are used in our proposed scheme. The experimental results show that the proposed method Is about l1~14% faster than the nearest neighbor method which is a wellknown conventional fast scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1433-1443
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• 1993

DCT(Discrete Cosine Transform) / IDCT(Inverse DCT) is widely used in various image compression and decompression systems as well as in DSP(Digital Signal Processing) applications. Since DCT/ IDCT is one of the most complicated part of the compression system, the performance of the system can be greatly enchanced by improving the speed of DCT/IDCT operation. In this thesis, we designed a DCT/IDCT core processor using module generator technique. By utilizing the partial sum and DA(Distributed Arithmetic) techniques, the DCT/ IDCT core processor is designed within small area. It is also designed to perform the IDCT(Inverse DCT) operation with little additional circuitry. The pipeline structure of the core processor enables the high performance, and the high accuracy of the DCT/IDCT operation is obtained by having fewer rounding stages. The proposed design is independent of design rules, and the number of the input bits and the accuracy of the internal calculation coa be easily adjusted due to the module generator technique. The accuracy of the processor satisfies the specifications in CCITT recommendation H, 261.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.6
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• pp.1229-1235
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• 2003

When finite length image signal is decomposed into 2-band signal and synthesized using 2-band orthogonal wavelet transform, boundary signals are not reconstructed perfectly. To reconstruct them perfectly, the filters which are different from wavelet filter are applied to the boundary signals. Since the existing boundary filters show poor frequency characteristic, the improvement of performance is bounded in practical applications. In this paper, the design method of improvement of frequency characteristic is proposed using inserting a zero to boundary filters which can reconstruct the boundary regions perfectly. Even though the length of proposed boundary filters is shorter, they show 4.2dB∼6.59dB gains in pass band and stop band error power compared with existing boundary filters. But synthesis process is some complicated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.767-773
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• 2017

In this paper, we propose a design of Intra prediction angular mode decision for HEVC encoder. Intra prediction coding of HEVC is a method for predicting a current block by referring to samples reconstructed around a current block. Intra prediction supports a total of 35 modes with 1 DC mode, 1 Planar mode, and 33 Angular modes. Intra prediction coding of HEVC works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original pixel, using an algorithm that determines angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9K and operating speed is 2GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.774-780
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• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.24-30
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• 2010

In this paper, we described intra prediction which is the one of techniques to be used for higher compression performance in H.264/AVC and proposed the design of intra predictor for efficient intra prediction mode processing. The proposed system is consist of processing elements, precomputation processing elements, an intra prediction controller, an internal memory and a register controller. The proposed system needs the reduced the computation cycles by using processing elements and precomputation processing element and also needs the reduced the number of access time to external memory by using internal memory and registers architecture. We designed the proposed system with Verilog-HDL and verified with suitable test vectors which are encoded YUV files. The proposed architecture belongs to the baseline profile of H.264/AVC decoder and is suitable for portable devices such as cellular phone with the size of $176{\times}144$. As a result of experiment, the performance of the proposed intra predictor is about 60% higher than that of the previous one.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.734-741
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• 2012

A new lossless intra coding method based on residual transform is applied to the next generation video coding standard HEVC (High Efficiency Video Coding). HEVC includes a multi-directional spatial prediction method to reduce spatial redundancy by using neighboring samples as a prediction for the samples in a block of data to be encoded. In the new lossless intra coding method, the spatial prediction is performed as samplewise DPCM (Difference Pulse Code Modulation) but is implemented as block-based manner by using residual transform and secondary residual transform on the HEVC standard. Experimental results show that the new lossless intra coding method reduces the bit rate by approximately 6.45% in comparison with the lossless intra coding method previously included in the HEVC standard.

• Journal of Broadcast Engineering
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• v.19 no.3
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• pp.307-315
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• 2014

A new modified lossless intra-coding method based on a cross residual transform is applied to HEVC(High Efficiency Video Coding). The HEVC standard including a multi-directional spatial prediction method to reduce spatial redundancy encodes the pixels in a PU (Prediction Unit) by using neighboring pixels. In the new modified lossless intra-coding method, the spatial prediction is performed by pixel-based DPCM but is implemented by block-based manner by using cross residual transform on the HEVC standard. The experimental results show that the new lossless intra-coding method reduces the bit rate of approximately 8.4% in comparison with the lossless-intra coding method in the HEVC standard and the proposed method results in slightly better compression ratio than the JPEG2000 lossless coding.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Journal of Korea Spatial Information System Society
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• v.4 no.1 s.7
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• pp.15-25
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• 2002

The OGC(OpenGIS Consortium), which is standardization organization of geographic data, have been studied standard for geographic data such as GML and GML based annotation for image and map. Annotation for map is applicable in various ways, understanding about geographic data, decision making and exchange of communication. For instance, Map annotation can be used for highlighting tour-course as symbols or explaining it as text on a map in tourism. This study suggests some annotation methodology for national digital map and presents a simple implementation of it. Firstly, this study suggests a way of updating OGC annotation schema which corresponds with DXF format and creating a GML application schema using the updated OGC annotation schema. Also it suggest a way of converting instance documents of annotated map to VML document with XSLT and VML for display. Later, it is needed to study for supporting another formats as well as DXF format. In addition, it is needed to study for managing the history of updated map entity with annotation in Local governments UIS(Urban Information System) in practical aspects.