• Journal of Broadcast Engineering
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• v.2 no.2
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• pp.86-93
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• 1997

Fast growth of multimedia applications requires new functions for video data processing. such as obj;cted-based video representation and manipulation. which are not supported by 11PEG-l and 11PEG-2. To support these requirements. 11PEG-4 video coding allows users to manipulate every video object easily by decomposing a scene into several video objects and coding each of them independently. However. the large amount of computations and flexible structure of 11PEG-4 video CODEC make it difficult to be implemented by either the general purpose DSP or a dedicated VLSI. In this paper, we propose a hardware architecture using a hybrid of a high performance programmable DSP and an application specific IC to implement a flexible 11PEG-4 video codec requiring the large amount of computations. The application specific IC has the functions of motion estimation and compensation.

• Journal of Broadcast Engineering
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• v.20 no.1
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• pp.16-25
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• 2015

Even if the demands for ultra-high-quality multimedia contents are increasing, it is difficult to produce, encode, play and transport ultra-high-quality contents under the existing broadcasting environment. By the reason, various technologies for the UHD contents have been developed in order to satisfy the user's needs. In this paper, we propose a design methodology of a broadcasting system, which consists of two parts, for UHD services with two parts. At the transmit part of the proposed system can encode a video into several layered-bitstreams hierarchically, and then transport each bitstream over heterogeneous networks. The receiver part can play the received video by composing the separated bitstreams. The proposed system can adaptively provide both HD and UHD contents according to user's reception conditions by using the heterogeneous networks.

• The KIPS Transactions:PartB
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• v.9B no.3
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• pp.343-350
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• 2002

A scene change detection which involves finding a cut between two consecutive shots is an important step for video indexing and retrieval. This paper proposes an algorithm for fast and accurate detection of abrupt scene changes in an MPEG compressed domain with minimal decoding requirements arid computational effort. The proposed method compares two successive DC images of I-frames for finding the GOP (group of picture) which contain a scene change and uses macroblock-coded type information contained in B-frames to detect the exact frame where the scene change occurred. The experiment results demonstrate that the proposed algorithm has better detection performance, such as precision and recall rate, than the existing method using all DC images. The algorithm has the advantage of speed, simplicity and accuracy. In addition, it requires less amount of storage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.102-111
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• 2005

In this paper, we propose an advanced hardware architecture for the fast inter prediction engine of the video coding standard MPEG-4 AVC. We describe the algorithm and derive the hardware architecture emphasizing and real time operation of the quarter_pel based motion estimation. The fast inter prediction engine is composed of block segmentation, motion estimation, motion compensation, and the fast quarter_pel calculator. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur & Virtex2 FPGA, and also by synthesis on Samsung 0.18 um CMOS technology. The synthesis result shows that the proposed hardware can operate at 62.5MHz. In this case, it can process about 88 QCIF video frames per second. The hardware is being used as a core module when implementing a complete MPEG-4 AVC video encoder chip for real-time multimedia application.

• Journal of Broadcast Engineering
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• v.6 no.2
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• pp.121-130
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• 2001

We propose an efficient DCT-domain video transcoding algorithm for flexible for bit-rate video communications. Video transcoding provides communication fiexibility by adaptively changing the bit-rate of compressed bit stream. During the transcoding process, adrift error is unavoidable because of the difference between reference images in the series of encoding and decoding. For solving the drift error problem, cascade pixel-domain transcoder (CPDT) has been proposed. CPDT, however, requires highly complex hardware and heavy computational overhead. In this paper we propose a DCT-domain transcoding technique, which enables efficient transcoding without any drift error. The proposed cascade DCT-domain transcoder (CDDT) is realized by new motion compensation and down-sampling methods in the DCT-domain.

• Journal of Broadcast Engineering
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• v.8 no.3
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• pp.288-296
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• 2003

ATSC (Advanced Television System Committee) has specified 18 video formats for DTV (Digital Television), e.g., scan format, size format, and frame rate format conversion. Effective MPEG-2 video transcoders should support any conversion between the above-mentioned formats. Scan format conversion Is hard to Implement because it may often induce frame rate and size format conversion together. Especially. because of picture type conversion caused by scan format conversion, the computational burden of motion estimation (ME) in transcoding becomes serious. This paper proposes a fast ME algorithm for MPEG-2 video transcoding supporting scan format conversion. Firstly, we extract and compose a set of candidate motion vectors (MVs) from the input bit-stream to comply with the re-encoding format. Secondly, the best MV is chosen among several candidate MVs by using a weighted median selector. Simulation results show that the proposed ME algorithm provides outstanding PSNR performance close to full search ME, while reducing the transcoding complexity significantly.

• The Journal of the Korea Contents Association
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• v.13 no.6
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• pp.20-29
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• 2013

The compression of video data is intended for real-time transmission of band-limited channels. Compressed video bit-streams are very sensitive to transmission error. If we lose packets or receive them with errors during transmission, not only the current frame will be corrupted, but also the error will propagate to succeeding frames due to the spatio-temporal predictive coding structure of sequences. Error detection and concealment is a good approach to reduce the bad influence on the reconstructed visual quality. To increase concealment efficiency, we need to get some more accurate error detection algorithm. In this paper, We hide specific data into the motion vector difference of each macro-block, which is obtained from the procedure of inter prediction mode in H.264/AVC. Then, the location of errors can be detected easily by checking transmitted specific data in decoder. We verified that the proposed algorithm generates good performances in PSNR and subjective visual quality through the computer simulation by H.324M mobile simulation tool.

• Journal of Broadcast Engineering
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• v.3 no.1
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• pp.85-92
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• 1998

The block matching algorithm is the most popular motion estimation method in image sequence coding. In this paper, we propose a VLSI architecture. for implementing a recently proposed fast bolck matching algorith, which uses spatial correlation of motion vectors and hierarchical searching scheme. The proposed architecture consists of a basic searching unit based on a systolic array and two shift register arrays. And it covers a search range of -32~ +31. By using the basic searching unit repeatedly, it reduces the number of gatyes for implementation. For basic searching unit implementation, a proper systolic array can be selected among various conventional ones by trading-off between speed and hardware cost. In this paper, a structure is selected as the basic searching unit so that the hardware cost can be minimized. The proposed overall architecture is fast enough for low bit-rate applications (frame size of $352{\times}288$, 3Oframes/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic searching unit, the architecture can be used for the higher bit-rate application of the frame size of $720{\times}480$ and 30 frames/sec.

• The Journal of the Korea Contents Association
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• v.9 no.2
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• pp.1-9
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• 2009

In this paper, we propose the efficient processing technique for unavailable data in hardware implementation of motion estimator in H.264/AVC with parallel processing architecture. Motion estimation processing in the hardware is generally based on pipe-lining, some MV data of neighbor blocks are not available, whereas all MV data are valid in software processing where the data are sequentially processed. In this paper, we solve the problem of data being unavailable in MVp computation. To minimize the quality degradation caused by unavailable MVs, in the proposed method, the unavailable MV of a neighboring block is replaced with an integer pel unit MV, an MVp of neighboring blocks, or an MVcol (MV of co-located block). Comparing to the conventional method [7], our method outperformed maximally 0.832dB and 0.179dB for QCIF and CIF, respectively, in terms of BDPSNR.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.5
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• pp.1189-1198
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• 2015

Recently, with rapid development of digital broadcasting technology, high-definition video service increased interest and demand. supplied mobile and image device support that improve 4~16 time existing Full HD. Such as high-definition contents supply, proposed compression for high-efficiency video codec (HEVC). Therefore, watermarking technology is necessary applying HEVC for protecting ownership and intellectual property. In this paper, analysis of prediction mode in intra frame and study feasibility of watermarking in re-encoding based HEVC. Proposed detect un-changed blocks in intra frame, using the result of analysis prediction mode.