• Journal of the Korean Geotechnical Society
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• v.17 no.6
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• pp.163-171
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• 2001

It is important to pay careful attention to the backfill construction for the structural integrity of concrete box culvert. To increase the structural integrity of culvert good compaction by the dynamic compaction roller with big capacity is as effective as good backfill materials. However structural distress of the culvert could be occurred due to the excessive earth pressure by great dynamic compaction load. In this study, two box culverts were constructed with change compaction materials and construction methods. Two type of on-site soils such as subbase and subgrade materials were used as backfill materials. In most case, dynamic compaction rollers with 11 to 12 ton weights were used and vibration frequency were applied from 2000 to 2500 rpm for the great compaction energy. Backfill compactions with good quality soils were carried out to examine the effect of cushions on dynamic lateral soil pressure. Expanded polystyrene (EPS) and rubber of tire were adapted as cushion materials and they are set on the culverts before backfill construction. This paper presents the main results on the characteristics of dynamic earth pressures. Test result indicates that the amounts of increased dynamic pressures are affected with backfill materials, depth of pressure cell, and compaction condition. The earth pressure during compaction can give harmful effect to box culvert because the value of dynamic earth pressure coefficient $(\DeltaK_{dyn}=\DeltaK\sigma_h\DeltaK\sigma_v)$ during compaction is greater than that of static condition. It was observed that cushion panels of EPS(t=10cm) and rubber(t=5cm) are effective to mitigate dynamic lateral pressure on the culverts.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.26-31
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• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• Journal of Intelligence and Information Systems
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• v.9 no.1
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• pp.157-177
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• 2003

This paper presents a comprehensive and successful application of data mining methodologies to improve and predict wafer yield in a semiconductor wafer fabrication system. As the wafer fabrication process is getting more complex and the volume of technological data gathered continues to be vast, it is difficult to analyze the cause of yield deterioration effectively by means of statistical or heuristic approaches. To begin with this paper applies a clustering method to automatically identify AUF (Area Uniform Failure) phenomenon from data instead of naked eye that bad chips occurs in a specific area of wafer. Next, sequential pattern analysis and classification methods are applied to and out machines and parameters that are cause of low yield, respectively. Furthermore, radial bases function method is used to predict yield of wafers that are in process. Finally, this paper demonstrates an information system, Y2R-PLUS (Yield Rapid Ramp-up, Prediction, analysis & Up Support), that is developed in order to analyze and predict wafer yield in a korea semiconductor manufacturer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.778-784
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• 2012

A symmetric block cryptosystem uses an identical cryptographic key at encryption and decryption processes. HIGHT cipher algorithm is 64-bit block cryptographic technology for mobile device that was authorized as international standard by ISO/IEC on 2010. In this paper, block cipher HIGHT algorithm is designed using Verilog-HDL. Four modes of operation for block cipher such as ECB, CBC, OFB and CTR are supported. When continuous message blocks of fixed size are encrypted or decrypted, the desigend HIGHT core can process a 64-bit message block in every 34-clock cycle. The cryptographic processor designed in this paper operates at 144MHz on vertex chip of Xilinx, Inc. and the maximum throughput is 271Mbps. The designed cryptographic processor is applicable to security module of the areas such as PDA, smart card, internet banking and satellite broadcasting.

• Korean Chemical Engineering Research
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• v.48 no.4
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• pp.470-474
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• 2010

In this study, we presents a simple microfluidic approach for generating uniform Poly(ethylene glycol)(PEG) microfiber. Elongated flow pattern of monomer induced by sheath flow of immiscible oil as continuous phase is generated in Y-shape junction and in situ polymerization by UV exposure. For uniform microfiber, we investigate the optimized flow condition and draw phase diagram as function of Ca and Qd. At the region for stable elongated flow pattern, the microfiber generated in microfluidic chip is very uniform and highly reproducible. Importantly, the thickness of microfibers can be easily controlled by flow rate of continuous and disperse phase. We also demonstrate the feasibility for biological application as encapsulating FITC-BSA in PEG microfiber.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.49-58
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• 1999

This paper describes an integrated low pass filter fabricated by using $0.8{\mu}m$ single poly CMOS ASIC technology. The filter has been designed for a 5th-order elliptic switched capacitor filter with cutoff frequency of 5khz, 0.1dB passband ripple. The filter consists of MOS swiches poly capacitors and five CMOS op-amps. For the realization of the SC filter, continuous time transfer function H(s) is obtained from LC passive type, and transfered as discrete time transfer H(z) through bilinear-z transform. Another filter has been designed by capacitor scaling for reduced chip area, considering dynamic range of the op-amp. The test results of two fabricated filters are cutoff frequency of 4.96~4.98khz, 35~38dB gain attenuation and 0.72~0.81dB passband ripple with the ${\pm}2.5V$power supply clock of 50KHz.

• Korean Chemical Engineering Research
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• v.52 no.1
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• pp.106-112
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• 2014

Here, we demonstrated the optimum design of pillar microstructure for efficient microdroplet merging. The microfluidic device mainly consisted of programmable microvalves and pillar microstructures. Based on the system, aqueous droplets were continuously generated at T-junction using actuating of integrated programmable microvalaves under the immiscible continuous fluid (mineral oil containing 0.5 wt% Span 80). The principle of merging process depended on the competitive correlation of hydraulic pressure of continuous phase and Laplace pressure of the droplet. We found that the design of the micropillars controls above two pressures. Finally, it was demonstrated that the microfluidic system could be able to efficient biochemical reaction. We expect that the microfluidic system is useful analytical or reaction tools in fundamental science, biotechnology, and chemical engineering.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.4
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• pp.25-34
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• 2000

In this paper, we first investigate the effect of residual code phase offset on the DS/CDMA code acquisition scheme. When the code phase offset normalized to the chip duration is within the advancing step size, the sum of two successive matched filter outputs has a constant value regardless of the residual code phase offset if noise is absent. Based on this observation, we propose a new code acquisition scheme, and investigate the performance of the scheme. The Proposed code acquisition scheme is analyzed, and numerical results are given to show that the proposed scheme is more robust to the variation of the residual code phase offset and has better performance than the conventional scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1186-1192
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• 2005

In this paper, we propose a novel channel estimation method based on pilot channel in a frequency interleaved multicarrier code division multiple access (MC-CDMA). Using the chip interleaving (CI) technique in the frequency domain make it possible to achieve higher frequency diversity gain than the system with conventional symbol interleaving. However, in CI-MC-CDMA systems, a pilot channel-based channel estimation (PCCE) cannot be applied because the orthogonality between pilot symbols and the data symbol is not maintained. The proposed method alters the system structure in order to maintain orthogonality between data and pilot channels over two consecutive subcarriers. Therefore, it can obtain accurate channel state information (CSI) in CI-MC-CDMA.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.