• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.320-323
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• 2010

This paper proposes efficient log and exponent calculation methods using a dual phase instruction set without additional ALU unit for a mobile enviroment. Using the Dual Phase Instruction set, it extracts exponent and mantissa from expression of floating point and calculates 24bit single precision floating point of log approximation using the Taylor series expansion algorithm. And with dual phase instruction set, it reduces instruction excution cycles. The proposed Dual Phase architecture reduces the performance degradation and maintain smaller size.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.288-294
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• 2000

In this paper, an efficient detail extraction technique for a progressive coding scheme is proposed. The existing technique using the top-hat transformation yields an efficient extraction scheme for isolated and visually important details, but yields an inefficient results containing significant redundancy extracting the contour information. The proposed technique using the strong edge feature extraction property of the morphological Laplacian in this paper can reduce the redundancy, and thus provides lower bit-rate. Experimental results show that the proposed technique is more efficient than the existing one, and promise the applicability of the morphological Laplacian operator.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.3
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• pp.511-514
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• 2019

Elliptic Curves Cryptosystem(ECC) provides the same level of security with relatively small key sizes, as compared to the traditional cryptosystems. The performance of ECC over GF(2m) and GF(p) depends on the efficiency of finite field arithmetic, especially the modular multiplication which is based on the reduction algorithm. In this paper, we propose a new modular reduction algorithm which provides high-speed ECC over NIST prime P-256. Detailed experimental results show that the proposed algorithm is about 25% faster than the previous methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.233-239
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• 2001

Among the operations in frequency domain for ADSL G.LITE Modem to perform, FFT and FEQ are most computation-intensive part, of which many researches have been focused on the efficient implementation. Previous papers suggested hardwares suitable for ADSL G.DMT system, which is not feasible for simple G.LITE system. The analysis of frequency domain operations and computational efficiency according to the allocation of hardware resources is performed in this paper. The suggested processor has the structure of one real multiplier and two real adders connected in parallel, which can perform the operations efficiently through the pipeline- and/or parallel-type job scheduling. The suggested processor uses less hardware resources than Kiss\`s ALU structure or FFT/IFFT processor suggested by Wang, so the suggested one is more suitable for G.LITE system than previous works.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1998.12a
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• pp.137-147
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• 1998

RSA 암호 시스템에서 512비트 이상의 큰 정수 소수의 모듈라 멱승 연산이 필요하기 때문에 효율적인 암호화 및 복호화를 위해서는 모듈라 멱승 연산의 고속 처리가 필수적이다. 따라서 본 논문에서는 몫을 추정하여 모듈라 감소를 실행하고 carry-save 덧셈과 중간 곱의 크기를 제한하는 interleaved 모듈라 곱셈 및 감소 기법을 이용하여 모듈라 멱승 연산을 수행하는 고속 모듈라 멱승 연산 프로세서를 논리 자동 합성 기법을 바탕으로 하는 탑다운 선계 방식으로 VHDL을 이용하여 모델링하고 SYNOPSIS 툴을 이용하여 합성 및 검증한 후 XILINX XC4025 FPGA에 구현하여 성능을 평가 및 분석한다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.688-690
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• 2004

플래시 메모리는 롬(ROM)의 특성과 램(RAM)의 특성, 저전력 등의 이점을 바탕으로 임베디드 시스템의 저장 장치로 많이 사용되고 있다. 그러나 특성상 읽기와 쓰기 연산의 속도가 많이 다르고, 쓰기 연산을 한번 수행한 부분에 다시 쓰기 연산을 하기 위해서는 먼저 지우기 연산을 수행해야 하고, 지울 수 있는 회수도 제한되어 있는 단점을 가지고 있다. 따라서 본 논문에서는 이런 특성들을 고려하여 저장 장치로서 플래시 메모리를 사용할 때 운영교제에서 최적화할 수 있는 부분 중 가상 메모리 시스템의 페이지 프레임 회수 기법을 최적화하여 쓰기와 지우기 연산의 수를 줄일 수 있는 방법을 제시한다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04b
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• pp.79-81
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• 2004

하나의 UDDI 노드에 저장된 웹 서비스 정보는 복제 연산을 통해 같은 레지스트리에 속한 다른 노드에도 똑같이 저장된다. 이러한 복제 연산은 change Record의 생성, 전송, 처리를 통해 수행된다. 그런데, 한 노드에서 성공적으로 처리된 연산이라도 복제 과정에서는 올바르게 동작하지 않을 수가 있다 본 논문에서는 기본적인 복제 과정 외에, 복제 연산 중에 발생한 에러의 발견 및 처리, 저널의 효율적인 관리, 키 생성 등의 문제를 해결하기 위한 방법을 제안하고 있다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.3
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• pp.27-34
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• 2003

Recently, an efficient hardware development for a cryptosystem is concerned. The efficiency of a multiplier for GF($2^n$)is directly related to the efficiency of some cryptosystem. This paper, considering the trade-off between time complexity andsize complexity, proposes a new multiplier architecture having n[n/2] AND gates and n([n/2]+1)- $$\Delta$_n$ = XOR gates, where $$\Delta$_n$=1 if n is even, $$\Delta$_n$=0 otherwise. This size complexity is less than that of existing ${multipliers}^{[5][12]}$which are $n^2$ AND gates and $n^2$-1 XOR gates. While a new multiplier is a serial-parallel multiplier to output a result of multiplication of two elements of GF($2^n$) after 2 clock cycles, the suggested multiplier is more suitable for some cryptographic device having space limitations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.47-52
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• 2009

H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory using efficient memory management for data reuse is necessary along with the high performance interpolators. We propose the architecture of a motion compensation unit for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and high performance interpolators with low complexity. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. We design a motion compensation unit and a intra-prediction unit and integrate them into a prediction unit and verify the operation and the performance.