• Title/Summary/Keyword: 연산 효율

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Implementation of Hardware Data Prefetcher Adaptable for Various State-of-the-Art Workload (다양한 최신 워크로드에 적용 가능한 하드웨어 데이터 프리페처 구현)

  • Kim, KangHee;Park, TaeShin;Song, KyungHwan;Yoon, DongSung;Choi, SangBang
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.12
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    • pp.20-35
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    • 2016
  • In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

Design and Implementation of Web GIS Server Using Node.js (Node.js를 활용한 웹GIS 서버의 설계와 구현)

  • Jun, Sang Hwan;Doh, Kyoung Tae
    • Spatial Information Research
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    • v.21 no.3
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    • pp.45-53
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    • 2013
  • Web GIS, based on the latest web-technology, has evolved to provide efficient and accurate spatial information to users. Furthermore, Web GIS Server has improved the performance constantly to respond user web requests and to offer spatial information service. This research aims to create a designed and implemented Web GIS Server that is named as Nodemap which uses the emergent technology, Node.js, which has been issued for an event-oriented, non-blocking I/O model framework for coding JavaScript on the server development. Basically, NodeMap is Web GIS Server that supports OGC implementation specification. It is designed to process GIS data by using DBMS, which supports spatial index and standard spatial query function. And NodeMap uses Node-Canvas module supported HTML5 canvas to render spatial information on tile map. Lastly, NodeMap uses Express module based connect module framework. NodaMap performance demonstration confirmed a possibility of applying Node.js as a (next/future) Web GIS Server development technology through the benchmarking. Having completed its quality test of NodeMap, this study has shown the compatibility and potential for Node.js as a Web GIS server development technology, and has shown the bright future of internet GIS service.

Performance Evaluation of SE-MMA Adaptive Equalization Algorithm with Varying Step Size based on Error Signal's Nonlinear Transform (오차 신호의 비선형 변환을 이용한 Varying Step Size 방식의 SE-MMA 적응 등화 알고리즘의 성능 평가)

  • Lim, Seung-Gag
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.17 no.1
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    • pp.77-82
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    • 2017
  • This paper related with the VSS_SE-MMA (Varying Step Size_Signed Error-MMA) which possible to improving the equalization performance that employing the varying adaptive step size based on the nonlinearities of error signal of SE-MMA (Signed Error-MMA), compensates the intersymbol interference by distortion occurs at the communication channel, in the transmitting the spectral efficient nonconstant modulus signal such as 16-QAM. The SE-MMA appeared to the reducing the computational arithematic operation using the polarity of error signal in the updating the tap coefficient of present MMA adaptive equalizer, but have a problem of equalization performance degradation. The VSS_SE-MMA improves the problem of such SE-MMA, using the varying step size consider the error signal in the update the adaptive equalizer tap coefficient, and its improved performance were confirmed by simulation. For this, the output signal constellation of equalizer, the residual isi and maximum distortion, MSE and SER were applied. As a result of computer simulation, it was confirmed that the VSS_SE-MMA algorithm has nearly same in convergence speed and has more good performance in every performance index at the steady state.

FPGA Implementation of a Grant Distribution Algorithm for the MAC in the ATM-PON (ATM-PON에서 MAC을 위한 승인분배 알고리즘의 FPGA 구현)

  • Kim, Tae-Min;Chung, Hae;Shin, Gun-Soon;Kim, Jin-Hee
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.10
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    • pp.1-9
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    • 2001
  • The MAC (Medium Access Control) protocol is needed for the OLT(Optical Line Termination) to allocate bandwidth to ONUs(Optical Network Units) and ONTs(Optical Network Terminations) dynamically in the ATM PON(Passive Optical Network). With the protocol, the OLT gathers ONUs' informations and provides grants efficiently to each ONU. Two important functions of the MAC protocol is the grant request procedure and the grant distribution algrithm. The latter has the greatest arithmetic portion in the TC(Transmission Convergence) module, occupies a relatively large portion of the overall chip area, has often been the limiting factor in terms of speed, and should be designed to guarantee the quality of service for various traffics. In this paper, we implement the MAC with the FPGA which can allocate grants dynamically according to the queue length information and the number of active ONUs and distribute grants uniformly to minimize the cell delay variation for each ONU. The structure of the MAC scheduler for the dynamic bandwidth assignment has a programmable look-up table. Also, it has a simple structure, the less chip area, and the lower delay time.

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A VLSI Design of High Performance H.264 CAVLC Decoder Using Pipeline Stage Optimization (파이프라인 최적화를 통한 고성능 H.264 CAVLC 복호기의 VLSI 설계)

  • Lee, Byung-Yup;Ryoo, Kwang-Ki
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.50-57
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    • 2009
  • This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

40Gb/s Foward Error Correction Architecture for Optical Communication System (광통신 시스템을 위한 40Gb/s Forward Error Correction 구조 설계)

  • Lee, Seung-Beom;Lee, Han-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.101-111
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    • 2008
  • This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

The impacts of CO2 tax on the regional economies in Korea (탄소세 도입이 지역경제에 미치는 영향에 대한 실증 분석)

  • Choi, Gyeong-Leob;Kim, Youngduk
    • Journal of Environmental Policy
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    • v.12 no.3
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    • pp.123-159
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    • 2013
  • We use a multi-regional dynamic computable general equilibrium model to explain an economic effect of $CO_2$ tax on the national and regional economy of Korea. First, we compare two $CO_2$ taxes: a region-specific $CO_2$ tax and a uniform $CO_2$ tax. In the region-specific tax, the $CO_2$ tax rate in the capital area and the south-eastern region is much greater than those in other regions. GDP loss resulting from the region-specific tax is bigger than that in the uniform tax. Second, we consider three options for tax recycling: consumption tax recycling, labor-income tax recycling, and corporate-income tax recycling. The corporate-income tax recycling has the least GDP-loss effect over the three options. These results support that it is more efficient to use a uniform $CO_2$ tax rate than a region-specific $CO_2$ tax rate and that the corporate-income tax recycling is more desirable in a sense of efficiency than the consumption and labor-income tax recycling options.

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A Secure Multipath Transmission Scheme Based on One-Way Hash Functions in Wireless Sensor Networks (무선 센서 네트워크 환경에서 단-방향 해쉬 함수 기반 다중 경로 보안 전송 기법)

  • Lee, Yun-Jeong;Kim, Dong-Joo;Park, Jun-Ho;Seong, Dong-Ook;Yoo, Jae-Soo
    • The Journal of the Korea Contents Association
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    • v.12 no.1
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    • pp.48-58
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    • 2012
  • With the development of sensing devices and wireless communication technologies, wireless sensor networks are composed of a large number of sensor nodes that are equipped with limited computing performance and restricted communication capabilities. Besides, the sensor nodes are deployed in hostile or unattended environments. Therefore, the wireless sensor networks are vulnerable to security. In particular, the fatal damage may be occurred when data are exposed in real world applications. Therefore, it is important for design requirements to be made so that wireless sensor networks provide the strong security. However, because the conventional security schemes in wired networks did not consider the limited performance of the sensor node, they are so hard to be applied to wireless sensor networks. In this paper, we propose a secure multipath transmission scheme based on one-way hash functions in wireless sensor networks considering the limited performance of the wireless sensor nodes. The proposed scheme converts a sensor reading based on one of one-way hash functions MD5 in order to make it harder to be cracked and snooped. And then, our scheme splits the converted data and transfers the split data to the base station using multi-path routing. The experimental results show that our proposed scheme consumes the energy of just about 6% over the existing security scheme.

Data Statical Analysis based Data Filtering Scheme for Monitoring System on Wireless Sensor Network (무선 센서 네트워크 모니터링 시스템을 위한 데이터 통계 분석 기반 데이터 필터링 기법)

  • Lee, Hyun-Jo;Choi, Young-Ho;Chang, Jae-Woo
    • The Journal of the Korea Contents Association
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    • v.10 no.3
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    • pp.53-63
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    • 2010
  • Recently, various monitoring systems are implemented actively by using wireless sensor networks(WSN). When implementing WSN-based monitoring system, there are three important issues to consider. At First, we need to consider a sensor node failure detection method to support the ongoing monitoring. Secondly, because sensor nodes use limited battery power, we need an efficient data filtering method to reduce energy consumption. At Last, a reducing processing overhead method is necessary. The existing Kalman filtering scheme has good performance on data filtering, but it causes too much processing overhead to estimate sensed data. To solve these problems, we, in this paper, propose a new data filtering scheme based on data statical analysis. First, the proposed scheme periodically aggregates node survival massages to support a node failure detection. Secondly, to reduce energy consumption, it sends the sample data with a node survival massage and do data filtering based on those messages. Finally, it analyzes the sample data to estimate filtering range in a server. As a result, each sensor node can use only simple compare operation for filtering data. In addition, we show from our performance analysis that the proposed scheme outperforms the Kalman filtering scheme in terms of the number of sending messages.

Implementation of OpenVG on Embedded Systems (임베디드 시스템을 위한 OpenVG 구현)

  • Lee, Hwan-Yong;Baek, Nak-Hoon
    • Journal of Korea Multimedia Society
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    • v.12 no.3
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    • pp.335-344
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    • 2009
  • Embedded systems and web browsers have started to provide two-dimensional vector graphics features, to finally support scalability of graphics outputs, while traditional graphics systems have focused on the raster and bitmap operations. Nowadays, SVG and Flash are actively used while OpenVG from Khronos group plays the role of a de facto low-level API standard to support them. In this paper, we represent the design and implementation process and the final results of an OpenVG implementation, AlexVG. From its design stage, our implementation aims at the cooperation with SVG-Tiny, another de facto standard for embedded systems. Currently, our overall system provides not only the OpenVG core features but also variety of OpenVG application programs and SVG-Tiny media file playing capabilities. For the conformance with the standard specifications, our system completely passed the whole OpenVG conformance test suites and the graphics output portions of the SVG-Tiny conformance test suites. From the performance point of view, we focused on the efficiency and effectiveness especially on the mobile phones and embedded devices with limited resources. As the result, it showed impressive benchmarks on the small-scale CPU's such as ARM's, even without neither any other libraries nor acceleration hardware.

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