• Journal of IKEEE
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• v.23 no.3
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• pp.925-933
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• 2019

In this paper, we implement ZYNQ SoC-based post-processing system that utilizes partial reconfiguration to remove blocking artifacts generated by compression algorithm. Hardware implementation of the deblocking filter in a Field Programmable Gate Array (FPGA) provides high computational capability and can be partially reconfigured to process 1080p images in real time. Partially reconfigurable areas in FPGA can be utilized to use hardware more efficiently in highly resource-constrained embedded systems. Experimental results of the proposed system show improvement of visual quality both objectively and subjectively with 0.6dB higher PSNR after deblocking filtering process. The measured power consumption of the deblocking filter during run-time is 68.33mW.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.5
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• pp.249-258
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• 2019

In the cyber-physical system, big data collected from numerous sensors and IoT devices is transferred to the Cloud for processing and analysis. When transferring data to the Cloud, merging data into one single file is more efficient than using the data in the form of split files. However, current merging and splitting operations are performed at the user-level and require many I / O requests to memory and storage devices, which is very inefficient and time-consuming. To solve this problem, this paper proposes kernel-level partitioning and combining operations. At the kernel level, splitting and merging files can be done with very little overhead by modifying the file system metadata. We have designed the proposed algorithm in detail and implemented it in the Linux Ext4 file system. In our experiments with the real Cloud storage system, our technique has achieved a transfer time of up to only 17% compared to the case of transferring split files. It also confirmed that the time required can be reduced by up to 0.5% compared to the existing user-level method.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.47 no.1
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• pp.75-80
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• 2019

In the recent aerospace and defence industries, it is required to develop small and low cost embedded systems. Based on a high speed digital signal processor (DSP), this paper first presents the development of an embedded system. To reduce the computation time of the high precision algorithm such as flight control, we also propose two algorithms for matrix multiplication. Validation results show that, compared to the performance using the $2{\times}2$ unit method, the performance of the proposed method 1 is improved, when the size of matrices is small. The proposed method 2 generally outperforms the $2{\times}2$ unit method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.319-322
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• 2019

There are many techniques for locating users in an indoor spot. Among them, WiFi fingerprinting technique which is widely used is phased into a data collection step and a positioning step. In the data collection step, all surrounding Wi-Fi signals are collected and managed as a list. The more data collected, the better the accuracy of the indoor position based on Wi-Fi fingerprint. Existing high-quality data collection and management methods are time consuming and costly, and many operations are required to extract and generate data necessary for machine learning. Therefore, we research how to collect and manage large amount of data in limited resources. This paper presents efficient data collection methods and data generation for learning.

• Annual Conference of KIPS
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• 2013.05a
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• pp.603-606
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• 2013

Machine to Machine (M2M) 통신은 수 많은 장비들이 우리 주변환경의 정보를 감지하여 상호간에 주고받는 방법을 활용한다. Third generation partnership project (3GPP)는 이러한 M2M 통신을 활용하여 유비쿼터스 환경과 자가인식형 서비스를 제공하려 하고 있다. 본 논문은 이러한 추세에 맞추어 새로운 개념의 통신인 3GPP M2M 통신의 시스템 구조, 특징들과 이에 대한 3GPP의 연구방향 등에 대한 튜토리얼로 사용될 수 있도록 하기 위해 작성되었다. 특히 M2M 통신에서의 특징들을 구체화하는 과정에서의 보안상 위협과 이에 대처하기 위한 요구사항들에 대해서 강조하였다. 이러한 보안상 위협을 제거하는 요구사항을 만족하면서 네트워크에 과부하를 가하지 않도록 하기 위한 그룹 기반의 최적화된 인증 프로토콜을 제안한다. 본 논문에서는 그룹을 기반으로 bilinear pairing을 사용하여 인증을 진행하며, 통신 딜레이를 줄이고 네트워크의 중심 장비에 과부하를 줄이기 위해 HSS(Home Subscriber Server)의 참여를 제한한 인증 및 키 동의 프로토콜을 제안하고, 이에 따른 연산 및 통신 오버헤드를 분석한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.37-44
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• 2001

In this paper, an efficient architecture for the ECC multiplier in GF(2") is proposed. We give a design example for the irreducible trinomials $x_{193}\;+\;x_{15}\;+\;1$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. A digit-serial multiplier with a digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The elliptic curve used in this implementation is defined by Weierstrass equations. The measured results show that the proposed multiplier it 0.3 times smaller than the bit-serial LFSR multiplier.lier.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.2
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• pp.75-84
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• 2008

Recently, the straightforward CRT-RSA was shown to be broken by fault attacks through many experimental results. In this paper, we analyze the fault attacks against CRT-RSA and their countermeasures, and then propose a new fault infective method resistant to the various fault attacks on CRT-RSA. In our CRT-RSA algorithm, if an error is injected in exponentiation with modulo p or q, then the error is spreaded by fault infective computation in CRT recombination operation. Our countermeasure doesn't have extra error detection procedure based on decision tests and doesn't use public parameter such as e. Also, the computational cost is effective compared to the previous secure countermeasures.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.3
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• pp.61-72
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• 2009

To guarantee security between the tag and back-end server and implementation efficiency in low power tag, we propose two typed mutual authentication protocols in RFID system. One is static-ID authentication scheme which is well suitable in distributed server environments. The other is dynamic-ID scheme which is additively satisfied forward security. In proposed scheme, it does not need any random number generator in tag and requires only one(maximally three) hash operation(s) in tag or server to authenticate each other. Furthermore, we implement the proposed schemes in RFID smart card system and verify its normal operations.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.5
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• pp.63-74
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• 2001

Modular exponentiation is an essential operation required for implementations of most public key cryptosystems. This paper presents two architectures for modular exponentiation using the Montgomery modular multiplication algorithm combined with two binary exponentiation methods, L-R(Left to Left) algorithms. The proposed architectures make use of MUXes for efficient pre-computation and post-computation in Montgomery\`s algorithm. For an n-bit modulus, if mulitplication with m carry processing clocks can be done (n+m) clocks, the L-R type design requires (1.5n+5)(n+m) clocks on average for an exponentiation. The R-L type design takes (n+4)(n+m) clocks in the worst case.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.3
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• pp.143-155
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• 2006

ARIA is a 128-bit block cipher, which became a Korean Standard in 2004. According to recent research, this cipher is attacked by first order DPA attack. In this paper, we propose a new masking technique as a countermeasure against first order DPA attack and apply it to the ARIA. The proposed method is suitable for low memory environment. By using this countermeasure, we verified that it is secure against first order DPA attack. In addition, our method based on precomputation of inverse table can reduce the computational cost as increasing the number of S-BOX masking.