• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.101-108
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• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show $61.02\%$ cell area reduction comparison with those of the conventional multiplier butterfly structure. furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show $46.1\%$ cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• The Journal of Society for e-Business Studies
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• v.11 no.2
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• pp.1-11
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• 2006

This paper proposes an efficient inversion algorithm for Galois field GF(2n) by using a modified multi-bit shifting method based on the Montgomery algorithm. It is well known that the efficiency of arithmetic algorithms depends on the basis and many foregoing papers use either polynomial or optimal normal basis. An inversion algorithm, which modifies a multi-bit shifting based on the Montgomery algorithm, is studied. Trinomials and AOPs (all-one polynomials) are tested to calculate the inverse. It is shown that the suggested inversion algorithm reduces the computation time up to 26 % of the forgoing multi-bit shifting algorithm. The modified algorithm can be applied in various applications and is easy to implement.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.7
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• pp.713-717
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• 2008

Recently, as the capacity of flash memory increases rapidly, efficient indexing methods become crucial for fast searching of a large volume of data stored in flash memory. Flash memory has its unique characteristics: the write operation is much more costly than the read operation and in-place updating is not allowed. In this paper, we propose a novel index structure that significantly reduces the number of write operations and thus supports efficient searches, insertions, and deletions. We verify the superiority of our method by performing extensive experiments.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.211-219
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• 2002

In this paper, a new architecture that can simultaneously process modular multiplication and squaring on GF(2$^{m}$ ) in m clock cycles by using the cellular automata is presented. This can be used efficiently for the design of the modular exponentiation on the finite field which is the basic computation in most public key crypto systems such as Diffie-Hellman key exchange, EIGamal, etc. Also, the cellular automata architecture is simple, regular, modular, cascadable and therefore, can be utilized efficiently for the implementation of VLSI.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.898-900
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• 2005

모듈러 멱승은 양수 x, E, N에 대하여 $x^Emod$ N로 정의된다. 모듈러 멱승 연산은 대부분의 공개키 암호화 알고리즘과 전자서명 프로토콜에서 핵심적인 연산으로 사용되고 있으므로, 그 효율성은 암호 프로토콜의 성능에 직접적인 영향을 미친다. 따라서 모듈러 멱승 연산에 필요한 곱셈 수를 감소시키기 위하여, 슬라이딩 윈도우를 적용한 CLNW 방법이나 VLNW 방법이 가장 널리 사용되고 있다. 본 논문에서는 조합론(combinatorics)에서 많이 응용되는 그래프 모델을 모듈러 멱승 연산에 적용할 수 있음을 보이고, 일반화된 그래프 모델을 통하여 VLNW 방법보다 더 적은 곱셈 수로 모듈러 멱승을 수행하는 방법을 설명한다. 본 논문이 제안하는 방법은 전체 곱셈 수를 감소시키는 새로운 블록들을 일반화된 그래프 모델의 초기 블록 테이블에 추가할 수 있는 초기 블록 테이블의 두 가지 확장 방법들로써, 접두사 블록의 확장과 덧셈 사슬 블록의 확장이다. 이 방법들은 새로운 블록을 초기 블록 테이블에 추가하기 위해 필요한 곱셈의 수와 추가한 뒤의 전체 곱셈 수를 비교하면서 초기 블록 테이블을 제한적으로 확장하므로, 지수 E에 non-zero bit가 많이 나타날수록 VLNW 방법에 비해 좋은 성능을 보이며 이는 실험을 통하여 검증하였다.

• Journal of KIISE:Databases
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• v.28 no.3
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• pp.494-511
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• 2001

In the environment that database management systems manage disk spaces for storing databases directly, this paper proposes a correct and efficient scheme of performing pending actions for the removal of database files. As for performing pending actions, upon performing recovery, the recovery process must identify unperformed pending actions of not-yet-terminated transactions and then perform those actions completely. Making the recovery process identify those actions through the analysis of log records in the log file is the basic idea of this paper. This scheme, as an extension of the execution of transactions, fuzzy checkpoint, and recovery of ARIES, uses the following methods: First, to identify not-yet-terminated transactions during recovery, transactions perform pending actions after writing 'pa_start'log records that signify both the commit of transactions and the start of executing pending actions, and then write 'eng'log records. Second, to restore pending-actions-lists of not-yet-terminated transactions during recovery, each transaction records its pending-actions-list in 'pa_start'log record and the checkpoint process records pending-actions-lists of transactions that are decided to be committed in 'end_chkpt'log record. Third, to identify the next pending action to perform during recovery, whenever a page is updated during the execution of pending actions, transactions record the information that identifies the next pending action to perform in the log record that has the redo information against the page.

• The KIPS Transactions:PartD
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• v.12D no.1 s.97
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• pp.13-20
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• 2005

The join operation is an important, fundamental operation in database systems, and it costs much to execute. In the literature, there are a number of technical attempts on development and evaluation of efficient join operations, all of which have been carried out In developers' perspective. This paper proposes a join operations benchmark that is dedicated to the evaluation of the join operations in database systems in users' perspective. This benchmark helps users select a database system that performs the join operations well in their work environment. The benchmark consists of 42 join queries, which are derived from on six performance factors that are picked out in two join categories. We have implemented this benchmark with two commercial database systems. The experimental results are also reported.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2861-2873
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• 1997

An FPU(Floating Point unit) is the principle component in high performance computer and is placed on a chip together with main processing unit recently. As a Processing speed of the FPU is accelerated, the rounding stage, which occupies one of the floating point Processing steps for floating point operations, has a considerable effect on overall floating point operations. In this paper, by studying and analyzing the processing flows of the conventional floating point adder/subtractor, multipler and divider, which are main component of the FPU, efficient rounding mechanisms are presented. Proposed mechanisms do not require any additional execution time and any high speed adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.10-18
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• 2004

Quadtree, which is a hierarchical data structure, is a very important data structure to represent binary images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The operations of unaligned linear quadtrees, which are operations among the linear quadtrees with different origin, are able to perform the translated or rotated images efficiently. And this operations requires alignment of the linear quadtrees. In this paper, we present an efficient algorithm to perform alignment of unaligned linear quadtrees, using three-dimensional $n{\pm}n{\pm}n$ processors on RMESH(Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to route the locational codes of quardtree on the hierarchical structure of $n{\pm}n{\pm}n$ RMESH.

• Spatial Information Research
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• v.10 no.1
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• pp.61-76
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• 2002

Mobile map services using PDA are prevailing because of the rapid developments of techniques of the internet and handhold devices recently. While the volume of spatial data is tremendous and the spatial operations are time-intensive, the PDA has small size memory and a low performance processor. Therefore, the spatial index for PDA should be small size and efficiently filter out the candidate objects of spatial operation as well. This paper proposes a spatial index far PDA called MHF(Multilevel Hashing File). The MHF has simple structure for storage efficiency and uses a hashing technique, which is direct search method, for search efficiency. This paper also designs a compression technique for MBR. which occupies almost 80% of index data in the two dimensional case. We call it HMBR. Although the HMBR technique reduces the MB\ulcorner size to almost a third, it shows good filtering efficiency because of no information loss by quantization in case of small objects that occupy a major portion. Our experimental tests show that the proposed MHF index using HMBR technique is appropriate for PDA in terms of the size of index, the Number of MBR comparisons, the filtering efficiency and the execution time of spatial operations.