• Journal of Korean Electronics
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• v.23 no.5
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• pp.94-98
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• 2003

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.60-60
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• 2001

칩과 칩 사이의 전송 속도가 증가함에 따라, 누화 및 스위칭 잡음에 의한 시스템의 성능 저하가 심각해지고 있다. 본 논문에서 제안하는 인터페이스는 한 심벌 펄스의 상승/하강 에지 위치에 데이터를 엔코딩하고, 천이 방향이 반대인 P-CTR과 N-CTR (positive/Negative Constant Transition Rate)을 사용하며, P-CTR 드라이버 2개 묶음과 N-CTR 드라이버 2개 묶음을 교대로 배치하여 버스를 구성한다. 제안하는 P/N-CTR 코드 인터페이스에서는 임의의 한 배선에 대해서 양옆의 이웃한 배선 신호가 동시에 같은 방향으로 스위칭하는 경우가 발생하지 않기 때문에 최대 누화 잡음과 최대 스위칭 잡음을 기존의 I/O 인테페이스 보다 감소시킬 수 있다. 제안하는 인터페이스 방식의 잡음 감소 특성을 검증하기 위하여 다양한 배선 구조와 여러 비트 폭의 버스 구조에 적용하고, 0.35㎛ SPICE 파라미터를 이용한 HSPICE 시뮬레이션을 수행하였다. 제안한 인터페이스는 기존의 인터페이스와 비교하여 32 비트 미만의 버스에서는 최대 누화 잡음이 최소26.78 % 감소하고, 누화는 50 % 감소한다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.302-312
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• 2001

As the data transfer rate between chips gets higher, both crosstalk and SSN (Simultaneous Switching Noise) deteriorate seriously the performance of a system. The proposed interface scheme uses P-CTR and N-CTR(Positive/Negative Constant Transition Rate) which encodes data at both falling and rising edges, where the transition directions of N-CTR and P-CTR are opposite. And the proposed bus system places two P-CTR drivers and two N-CTR drivers alternatively. In the proposed P/N-CTR interface scheme, the signals of neighboring interconnection lines at both sides of a bus will not switch simultaneously in the same direction, which leads to reduction in the maximum crosstalk and SSN compared to conventional interfaces. For verification of noise reduction of the proposed interface scheme, the scheme is applied to several kinds of bit-wide buses with various interconnection structures, and HSPICE simulation was performed with 0.35 ${\mu}{\textrm}{m}$ SPICE parameters. The simulation results show that in the 32-bit or less wide bus, the maximum SSN and crosstalk are reduced to at least 26.78% and 50%, respectively in comparison with the conventional interface scheme.